From patchwork Fri Mar 17 06:46:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9629905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BA12660245 for ; Fri, 17 Mar 2017 06:49:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA1F028698 for ; Fri, 17 Mar 2017 06:49:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F3A62869C; Fri, 17 Mar 2017 06:49:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3AE7F28698 for ; Fri, 17 Mar 2017 06:49:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coleu-0000Yu-UX; Fri, 17 Mar 2017 06:46:44 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1colet-0000XT-T3 for xen-devel@lists.xen.org; Fri, 17 Mar 2017 06:46:43 +0000 Received: from [85.158.137.68] by server-7.bemta-3.messagelabs.com id 2E/6A-23854-3568BC85; Fri, 17 Mar 2017 06:46:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRWlGSWpSXmKPExsVywNxEWzeo7XS EweH5ehZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bvc2+YC3apVEw484WlgXGBTBcjJ4eQQIXE 0qlXWUBsCQFeiSPLZrBC2AES1yfeYepi5AKq6WWU2Nv3kQ0kwSagL7Hi8UGwIhEBaYlrny8zg tjMAtUSE6fPAbOFBRwkNp9eDdTMwcEioCpxfW4MiMkrYCtx5EYOxHh5iQtXT4Gt5RSwk/jYeI sF4hxbicaG20wTGHkXMDKsYlQvTi0qSy3SNdVLKspMzyjJTczM0TU0MNbLTS0uTkxPzUlMKtZ Lzs/dxAgMhHoGBsYdjJe/Oh1ilORgUhLlVRE8ESHEl5SfUpmRWJwRX1Sak1p8iFGGg0NJgld8 PlBOsCg1PbUiLTMHGJIwaQkOHiURXluQNG9xQWJucWY6ROoUo6KUOO/VeUAJAZBERmkeXBssD i4xykoJ8zIyMDAI8RSkFuVmlqDKv2IU52BUEuZ1BhnPk5lXAjf9FdBiJqDFiT+PgCwuSURIST UwsppN+RbNYGJ/Lid1TpZRnPzqiap77omzFH/bySD+s0DsUrNffKF8qmR2vbvFlCv/laxkkna Wyt+cXd/Q4cez4Ggya1HbnRJn+R+HIwXCtr5bcu/I65z/riLn0nWtL31/ILLze8Kdvn8bo5hM vY4pnj96PrrtCCN7x2t1jxmXmP8cUvzsVmShxFKckWioxVxUnAgAcOPK7X4CAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-11.tower-31.messagelabs.com!1489733199!59832828!2 X-Originating-IP: [192.55.52.43] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12149 invoked from network); 17 Mar 2017 06:46:42 -0000 Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by server-11.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Mar 2017 06:46:42 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 23:46:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,175,1486454400"; d="scan'208"; a="1109452643" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by orsmga001.jf.intel.com with ESMTP; 16 Mar 2017 23:46:39 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Mar 2017 14:46:09 +0800 Message-Id: <20170317064614.23539-8-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170317064614.23539-1-haozhong.zhang@intel.com> References: <20170317064614.23539-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v2 07/12] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest to read/write MSR_IA32_MCG_EXT_CTL. Signed-off-by: Haozhong Zhang --- Cc: Jan Beulich Cc: Andrew Cooper Changes in v2: * Remove stray blank in the code comment. * Move the success branch to the front when handling MSR_IA32_MCG_EXT_CTL. * Move lmce_enabled before bank[] in struct vmce. * Increase XEN_DOMCTL_INTERFACE_VERSION by 1. --- xen/arch/x86/cpu/mcheck/vmce.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-x86/mce.h | 1 + xen/include/public/arch-x86/hvm/save.h | 2 ++ xen/include/public/domctl.h | 2 +- 4 files changed, 37 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 058bb91..c396d07 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -90,6 +90,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt) v->arch.vmce.mcg_cap = ctxt->caps; v->arch.vmce.bank[0].mci_ctl2 = ctxt->mci_ctl2_bank0; v->arch.vmce.bank[1].mci_ctl2 = ctxt->mci_ctl2_bank1; + v->arch.vmce.lmce_enabled = ctxt->lmce_enabled; return 0; } @@ -199,6 +200,26 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_CTL %#"PRIx64"\n", cur, *val); break; + case MSR_IA32_MCG_EXT_CTL: + /* + * If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, the LMCE and LOCK + * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it + * does not need to check them here. + */ + if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + { + *val = cur->arch.vmce.lmce_enabled ? MCG_EXT_CTL_LMCE_EN : 0; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", + cur, *val); + } + else + { + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL, not supported\n", + cur); + } + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0; break; @@ -308,6 +329,16 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) mce_printk(MCE_VERBOSE, "MCE: %pv: MCG_CAP is r/o\n", cur); break; + case MSR_IA32_MCG_EXT_CTL: + if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && + !(val & ~MCG_EXT_CTL_LMCE_EN) ) + cur->arch.vmce.lmce_enabled = (val & MCG_EXT_CTL_LMCE_EN); + else + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: wr MCG_EXT_CTL %"PRIx64"%s\n", + cur, val, (ret == -1) ? ", not supported" : ""); + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_wrmsr(cur, msr, val) : 0; break; @@ -326,7 +357,8 @@ static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h) struct hvm_vmce_vcpu ctxt = { .caps = v->arch.vmce.mcg_cap, .mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2, - .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2 + .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2, + .lmce_enabled = v->arch.vmce.lmce_enabled, }; err = hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt); diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 6b827ef..dee66b3 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -28,6 +28,7 @@ struct vmce { uint64_t mcg_cap; uint64_t mcg_status; spinlock_t lock; + bool lmce_enabled; /* guest MSR_IA32_MCG_EXT_CTL.LMCE_EN (bit 0) */ struct vmce_bank bank[GUEST_MC_BANK_NUM]; }; diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 419a3b2..76374fc 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -599,6 +599,8 @@ struct hvm_vmce_vcpu { uint64_t caps; uint64_t mci_ctl2_bank0; uint64_t mci_ctl2_bank1; + uint8_t lmce_enabled; + uint8_t pad[7]; }; DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu); diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 85cbb7c..2842589 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -37,7 +37,7 @@ #include "hvm/save.h" #include "memory.h" -#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000c +#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000d /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation.