From patchwork Mon Mar 27 10:18:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 9646347 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3F8E60328 for ; Mon, 27 Mar 2017 10:20:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2C2C28364 for ; Mon, 27 Mar 2017 10:20:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C785328387; Mon, 27 Mar 2017 10:20:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 600F628364 for ; Mon, 27 Mar 2017 10:20:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1csRjc-00076L-9H; Mon, 27 Mar 2017 10:18:48 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1csRja-00073O-UJ for xen-devel@lists.xenproject.org; Mon, 27 Mar 2017 10:18:47 +0000 Received: from [193.109.254.147] by server-6.bemta-6.messagelabs.com id A8/CD-15112-607E8D85; Mon, 27 Mar 2017 10:18:46 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRWlGSWpSXmKPExsWyU9JRQpft+Y0 Igy2feC2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oyub72sBYs0K3p2X2BrYPwl38XIySEh4Cdx 59J+ZhCbTUBH4uLcnWxdjBwcIgIqErf3GoCYzALlEjNuxINUCAtESvR8e8cKYrMIqEo8+DgZr JNXwFLi75O7rBAT5SUebXoENoVTwEri7L4KkLAQUEnnvi52iHJBiZMzn7CA2MwCmhKt23+zQ9 jyEs1bZzND1CtK9M97wAYxMl1i4rMelgmM/LOQtM9C0j4LSfsCRuZVjBrFqUVlqUW6RhZ6SUW Z6RkluYmZObqGBmZ6uanFxYnpqTmJScV6yfm5mxiB4ccABDsYz68NPMQoycGkJMr74fSNCCG+ pPyUyozE4oz4otKc1OJDjDIcHEoSvNlPgXKCRanpqRVpmTnASIBJS3DwKInwHngClOYtLkjML c5Mh0idYlSUEuctBOkTAElklObBtcGi7xKjrJQwLyPQIUI8BalFuZklqPKvGMU5GJWEeTeDTO HJzCuBm/4KaDET0OLD88EWlyQipKQaGHkcXWbcji0+9rfy4LbqK8/O5x41L2L/GdblI6cQLbc iv2zexwWRLzcu2Hy2y0+8rfnol4SoizWt3nNPrdP19Ls7ue7YWcsbf9cV5tqFyZYyPBRc/3fX 6Qn2RyYGp1X1h303LTx0d+qzMIMjAvNibXlsfsyduF7gzWGn2+xx+74st+AK8oo/IajEUpyRa KjFXFScCADw0ng9uQIAAA== X-Env-Sender: prvs=25239713d=roger.pau@citrix.com X-Msg-Ref: server-8.tower-27.messagelabs.com!1490609913!83588185!5 X-Originating-IP: [185.25.65.24] X-SpamReason: No, hits=0.0 required=7.0 tests=received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27073 invoked from network); 27 Mar 2017 10:18:46 -0000 Received: from smtp.eu.citrix.com (HELO SMTP.EU.CITRIX.COM) (185.25.65.24) by server-8.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 27 Mar 2017 10:18:46 -0000 X-IronPort-AV: E=Sophos;i="5.36,231,1486425600"; d="scan'208";a="43158879" From: Roger Pau Monne To: Date: Mon, 27 Mar 2017 11:18:20 +0100 Message-ID: <20170327101823.99368-5-roger.pau@citrix.com> X-Mailer: git-send-email 2.12.1 In-Reply-To: <20170327101823.99368-1-roger.pau@citrix.com> References: <20170327101823.99368-1-roger.pau@citrix.com> MIME-Version: 1.0 X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) Cc: Andrew Cooper , Jan Beulich , Roger Pau Monne Subject: [Xen-devel] [PATCH v2 4/7] x86/vioapic: allow the vIO APIC to have a variable number of pins X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Although it's still always set to VIOAPIC_NUM_PINS (48). Add a new field to the hvm_ioapic struct to contain the number of pins (number of IO redirection table entries) and turn the redirection table into a variable sized array. Signed-off-by: Roger Pau Monné --- Cc: Jan Beulich Cc: Andrew Cooper --- Changes since v1: - Almost completely reworked due to previous changes. --- xen/arch/x86/hvm/vioapic.c | 28 +++++++++++++++++----------- xen/include/asm-x86/hvm/vioapic.h | 4 +++- 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c index 39dbf832b3..00048ad65d 100644 --- a/xen/arch/x86/hvm/vioapic.c +++ b/xen/arch/x86/hvm/vioapic.c @@ -53,7 +53,7 @@ static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic) case VIOAPIC_REG_VERSION: result = ((union IO_APIC_reg_01){ .bits = { .version = VIOAPIC_VERSION_ID, - .entries = VIOAPIC_NUM_PINS - 1 } + .entries = vioapic->nr_pins - 1 } }).raw; break; @@ -73,7 +73,7 @@ static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic) uint32_t redir_index = (vioapic->ioregsel - VIOAPIC_REG_RTE0) >> 1; uint64_t redir_content; - if ( redir_index >= VIOAPIC_NUM_PINS ) + if ( redir_index >= vioapic->nr_pins ) { gdprintk(XENLOG_WARNING, "apic_mem_readl:undefined ioregsel %x\n", vioapic->ioregsel); @@ -197,7 +197,7 @@ static void vioapic_write_indirect( HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "rte[%02x].%s = %08x", redir_index, vioapic->ioregsel & 1 ? "hi" : "lo", val); - if ( redir_index >= VIOAPIC_NUM_PINS ) + if ( redir_index >= vioapic->nr_pins ) { gdprintk(XENLOG_WARNING, "vioapic_write_indirect " "error register %x\n", vioapic->ioregsel); @@ -368,7 +368,7 @@ void vioapic_irq_positive_edge(struct domain *d, unsigned int irq) HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "irq %x", irq); - ASSERT(irq < VIOAPIC_NUM_PINS); + ASSERT(irq < vioapic->nr_pins); ASSERT(spin_is_locked(&d->arch.hvm_domain.irq_lock)); ent = &vioapic->redirtbl[irq]; @@ -397,7 +397,7 @@ void vioapic_update_EOI(struct domain *d, u8 vector) spin_lock(&d->arch.hvm_domain.irq_lock); - for ( gsi = 0; gsi < VIOAPIC_NUM_PINS; gsi++ ) + for ( gsi = 0; gsi < vioapic->nr_pins; gsi++ ) { ent = &vioapic->redirtbl[gsi]; if ( ent->fields.vector != vector ) @@ -431,9 +431,8 @@ static int ioapic_save(struct domain *d, hvm_domain_context_t *h) if ( !has_vioapic(d) ) return 0; - BUILD_BUG_ON(sizeof(struct hvm_hw_vioapic) != - sizeof(struct hvm_vioapic) - - offsetof(struct hvm_vioapic, base_address)); + if ( s->nr_pins != VIOAPIC_NUM_PINS ) + return -EOPNOTSUPP; return hvm_save_entry(IOAPIC, 0, h, &s->base_address); } @@ -445,6 +444,9 @@ static int ioapic_load(struct domain *d, hvm_domain_context_t *h) if ( !has_vioapic(d) ) return -ENODEV; + if ( s->nr_pins != VIOAPIC_NUM_PINS ) + return -EOPNOTSUPP; + return hvm_load_entry(IOAPIC, h, &s->base_address); } @@ -453,14 +455,16 @@ HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM); void vioapic_reset(struct domain *d) { struct hvm_vioapic *vioapic = domain_vioapic(d); + uint32_t nr_pins = vioapic->nr_pins; int i; if ( !has_vioapic(d) ) return; - memset(vioapic, 0, sizeof(*vioapic)); + memset(vioapic, 0, hvm_vioapic_size(nr_pins)); vioapic->domain = d; - for ( i = 0; i < VIOAPIC_NUM_PINS; i++ ) + vioapic->nr_pins = nr_pins; + for ( i = 0; i < nr_pins; i++ ) vioapic->redirtbl[i].fields.mask = 1; vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS; } @@ -471,10 +475,12 @@ int vioapic_init(struct domain *d) return 0; if ( (d->arch.hvm_domain.vioapic == NULL) && - ((d->arch.hvm_domain.vioapic = xmalloc(struct hvm_vioapic)) == NULL) ) + ((d->arch.hvm_domain.vioapic = + xmalloc_bytes(hvm_vioapic_size(VIOAPIC_NUM_PINS))) == NULL) ) return -ENOMEM; d->arch.hvm_domain.vioapic->domain = d; + d->arch.hvm_domain.vioapic->nr_pins = VIOAPIC_NUM_PINS; vioapic_reset(d); register_mmio_handler(d, &vioapic_mmio_ops); diff --git a/xen/include/asm-x86/hvm/vioapic.h b/xen/include/asm-x86/hvm/vioapic.h index e8ec0be7b6..df8154390f 100644 --- a/xen/include/asm-x86/hvm/vioapic.h +++ b/xen/include/asm-x86/hvm/vioapic.h @@ -49,13 +49,15 @@ struct hvm_vioapic { struct domain *domain; + uint32_t nr_pins; /* Layout below must match hvm_hw_vioapic. */ uint64_t base_address; uint32_t ioregsel; uint32_t id; - union vioapic_redir_entry redirtbl[VIOAPIC_NUM_PINS]; + union vioapic_redir_entry redirtbl[]; }; +#define hvm_vioapic_size(cnt) offsetof(struct hvm_vioapic, redirtbl[cnt]) #define domain_vioapic(d) ((d)->arch.hvm_domain.vioapic) #define vioapic_domain(v) ((v)->domain)