From patchwork Wed Mar 29 14:39:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 9651717 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2D243602BE for ; Wed, 29 Mar 2017 14:42:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22D9B205FC for ; Wed, 29 Mar 2017 14:42:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 170AE26E49; Wed, 29 Mar 2017 14:42:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DD544205FC for ; Wed, 29 Mar 2017 14:42:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctElO-0007as-1K; Wed, 29 Mar 2017 14:39:54 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctElM-0007aG-Ow for xen-devel@lists.xenproject.org; Wed, 29 Mar 2017 14:39:52 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id 46/EE-03642-837CBD85; Wed, 29 Mar 2017 14:39:52 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRWlGSWpSXmKPExsWyU9JRQtf8+O0 IgzWHVC2+b5nM5MDocfjDFZYAxijWzLyk/IoE1ow9l9ULmtwqJj89yd7AOMm8i5GTQ0LAT2Lr luMsIDabgI7Exbk72UBsEYFYicePtzB3MXJwMAuUS8y4EQ8SFhaIkti+YS8TiM0ioCrRcfsoK 0gJr4CFxJMFohAT9STeTnzBCGJzClhKrN32jh3EFgIq+fRtJdh0XgFBiZMzn4BtZRbQlGjd/p sdwpaXaN46mxmiXlGif94DNoiZ6RJb//5insDIPwtJ+ywk7bOQtC9gZF7FqF6cWlSWWqRrqZd UlJmeUZKbmJmja2hgppebWlycmJ6ak5hUrJecn7uJERh8DECwg/HupoBDjJIcTEqivCcMb0cI 8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuC1PQyUEyxKTU+tSMvMAcYBTFqCg0dJhDcDJM1bXJCYW 5yZDpE6xagoJc7LCJIQAElklObBtcFi7xKjrJQwLyPQIUI8BalFuZklqPKvGMU5GJWEee1Bpv Bk5pXATX8FtJgJaLG4zS2QxSWJCCmpBsa0p0eLuP5F6dav7TLxT9a7VtD273/kvkepk2ZmKp+ 0nXUm67j7w7fqq3//DH0vYqA0f8uhytKUpSvf3hPSFdecatGe+3Um91cXedGW1vtvTMx5b8v2 erjH3JTWuq+7b/WnxwvPTn/Qf0M26OvKaSabI36qBkbIsC7lZdjGcTt2TYazw+qygGQlluKMR EMt5qLiRADfJxCpuAIAAA== X-Env-Sender: prvs=25439209a=roger.pau@citrix.com X-Msg-Ref: server-3.tower-21.messagelabs.com!1490798390!57502653!2 X-Originating-IP: [185.25.65.24] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8332 invoked from network); 29 Mar 2017 14:39:51 -0000 Received: from smtp.eu.citrix.com (HELO SMTP.EU.CITRIX.COM) (185.25.65.24) by server-3.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 29 Mar 2017 14:39:51 -0000 X-IronPort-AV: E=Sophos;i="5.36,241,1486425600"; d="scan'208";a="43344036" From: Roger Pau Monne To: , , Date: Wed, 29 Mar 2017 15:39:11 +0100 Message-ID: <20170329143918.4445-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.11.0 (Apple Git-81) In-Reply-To: <20170329143918.4445-1-roger.pau@citrix.com> References: <20170329143918.4445-1-roger.pau@citrix.com> MIME-Version: 1.0 X-ClientProxiedBy: AMSPEX02CAS01.citrite.net (10.69.22.112) To AMSPEX02CL02.citrite.net (10.69.22.126) Cc: Andrew Cooper , Jan Beulich , Roger Pau Monne Subject: [Xen-devel] [PATCH v3 1/8] x86/vioapic: expand hvm_vioapic to contain vIO APIC internal state X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is required in order to have a variable number of vIO APIC pins, instead of the current fixed value (48). Note that this patch only expands the fields of the hvm_vioapic struct, without actually introducing any new fields or functionality. The reason to expand the hvm_vioapic structure instead of the hvm_hw_vioapic one is that the variable number of pins functionality is only going to be used by the hardware domain, so no modifications are needed to the save format. Signed-off-by: Roger Pau MonnĂ© Reviewed-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper --- Changes since v2: - Change patch title. - Use an unnamed struct to store the vioapic state inside of hvm_vioapic. - Use a define to declare the hvm_hw_vioapic struct (and the equivalent unnamed struct inside of hvm_vioapic). - Remove the BUILD_BUG_ON. Changes since v1: - New in this version. --- xen/arch/x86/hvm/vioapic.c | 39 +++++++++++++------------ xen/include/asm-x86/hvm/vioapic.h | 10 ++++--- xen/include/public/arch-x86/hvm/save.h | 53 ++++++++++++++++++++-------------- 3 files changed, 57 insertions(+), 45 deletions(-) diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c index fdbb21f097..23abdfc4c6 100644 --- a/xen/arch/x86/hvm/vioapic.c +++ b/xen/arch/x86/hvm/vioapic.c @@ -42,9 +42,9 @@ /* HACK: Route IRQ0 only to VCPU0 to prevent time jumps. */ #define IRQ0_SPECIAL_ROUTING 1 -static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq); +static void vioapic_deliver(struct hvm_vioapic *vioapic, int irq); -static uint32_t vioapic_read_indirect(const struct hvm_hw_vioapic *vioapic) +static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic) { uint32_t result = 0; @@ -94,7 +94,7 @@ static int vioapic_read( struct vcpu *v, unsigned long addr, unsigned int length, unsigned long *pval) { - const struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain); + const struct hvm_vioapic *vioapic = domain_vioapic(v->domain); uint32_t result; HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "addr %lx", addr); @@ -119,7 +119,7 @@ static int vioapic_read( } static void vioapic_write_redirent( - struct hvm_hw_vioapic *vioapic, unsigned int idx, + struct hvm_vioapic *vioapic, unsigned int idx, int top_word, uint32_t val) { struct domain *d = vioapic_domain(vioapic); @@ -170,7 +170,7 @@ static void vioapic_write_redirent( } static void vioapic_write_indirect( - struct hvm_hw_vioapic *vioapic, uint32_t val) + struct hvm_vioapic *vioapic, uint32_t val) { switch ( vioapic->ioregsel ) { @@ -215,7 +215,7 @@ static int vioapic_write( struct vcpu *v, unsigned long addr, unsigned int length, unsigned long val) { - struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain); + struct hvm_vioapic *vioapic = domain_vioapic(v->domain); switch ( addr & 0xff ) { @@ -242,7 +242,7 @@ static int vioapic_write( static int vioapic_range(struct vcpu *v, unsigned long addr) { - struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain); + struct hvm_vioapic *vioapic = domain_vioapic(v->domain); return ((addr >= vioapic->base_address && (addr < vioapic->base_address + VIOAPIC_MEM_LENGTH))); @@ -255,7 +255,7 @@ static const struct hvm_mmio_ops vioapic_mmio_ops = { }; static void ioapic_inj_irq( - struct hvm_hw_vioapic *vioapic, + struct hvm_vioapic *vioapic, struct vlapic *target, uint8_t vector, uint8_t trig_mode, @@ -275,7 +275,7 @@ static inline int pit_channel0_enabled(void) return pt_active(¤t->domain->arch.vpit.pt0); } -static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq) +static void vioapic_deliver(struct hvm_vioapic *vioapic, int irq) { uint16_t dest = vioapic->redirtbl[irq].fields.dest_id; uint8_t dest_mode = vioapic->redirtbl[irq].fields.dest_mode; @@ -361,7 +361,7 @@ static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq) void vioapic_irq_positive_edge(struct domain *d, unsigned int irq) { - struct hvm_hw_vioapic *vioapic = domain_vioapic(d); + struct hvm_vioapic *vioapic = domain_vioapic(d); union vioapic_redir_entry *ent; ASSERT(has_vioapic(d)); @@ -388,7 +388,7 @@ void vioapic_irq_positive_edge(struct domain *d, unsigned int irq) void vioapic_update_EOI(struct domain *d, u8 vector) { - struct hvm_hw_vioapic *vioapic = domain_vioapic(d); + struct hvm_vioapic *vioapic = domain_vioapic(d); struct hvm_irq *hvm_irq = &d->arch.hvm_domain.irq; union vioapic_redir_entry *ent; int gsi; @@ -426,38 +426,39 @@ void vioapic_update_EOI(struct domain *d, u8 vector) static int ioapic_save(struct domain *d, hvm_domain_context_t *h) { - struct hvm_hw_vioapic *s = domain_vioapic(d); + struct hvm_vioapic *s = domain_vioapic(d); if ( !has_vioapic(d) ) return 0; - return hvm_save_entry(IOAPIC, 0, h, s); + return hvm_save_entry(IOAPIC, 0, h, &s->domU); } static int ioapic_load(struct domain *d, hvm_domain_context_t *h) { - struct hvm_hw_vioapic *s = domain_vioapic(d); + struct hvm_vioapic *s = domain_vioapic(d); if ( !has_vioapic(d) ) return -ENODEV; - return hvm_load_entry(IOAPIC, h, s); + return hvm_load_entry(IOAPIC, h, &s->domU); } HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM); void vioapic_reset(struct domain *d) { - struct hvm_vioapic *vioapic = d->arch.hvm_domain.vioapic; + struct hvm_vioapic *vioapic = domain_vioapic(d); int i; if ( !has_vioapic(d) ) return; - memset(&vioapic->hvm_hw_vioapic, 0, sizeof(vioapic->hvm_hw_vioapic)); + memset(vioapic, 0, sizeof(*vioapic)); + vioapic->domain = d; for ( i = 0; i < VIOAPIC_NUM_PINS; i++ ) - vioapic->hvm_hw_vioapic.redirtbl[i].fields.mask = 1; - vioapic->hvm_hw_vioapic.base_address = VIOAPIC_DEFAULT_BASE_ADDRESS; + vioapic->redirtbl[i].fields.mask = 1; + vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS; } int vioapic_init(struct domain *d) diff --git a/xen/include/asm-x86/hvm/vioapic.h b/xen/include/asm-x86/hvm/vioapic.h index 745c09ab5c..ab7be9e741 100644 --- a/xen/include/asm-x86/hvm/vioapic.h +++ b/xen/include/asm-x86/hvm/vioapic.h @@ -48,13 +48,15 @@ #define VIOAPIC_REG_RTE0 0x10 struct hvm_vioapic { - struct hvm_hw_vioapic hvm_hw_vioapic; struct domain *domain; + union { + XEN_HVM_VIOAPIC(, VIOAPIC_NUM_PINS); + struct hvm_hw_vioapic domU; + }; }; -#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic->hvm_hw_vioapic) -#define vioapic_domain(v) (container_of((v), struct hvm_vioapic, \ - hvm_hw_vioapic)->domain) +#define domain_vioapic(d) ((d)->arch.hvm_domain.vioapic) +#define vioapic_domain(v) ((v)->domain) int vioapic_init(struct domain *d); void vioapic_deinit(struct domain *d); diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 66ae1a2b80..ab848f6467 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -361,30 +361,39 @@ DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic); * IO-APIC */ +union vioapic_redir_entry +{ + uint64_t bits; + struct { + uint8_t vector; + uint8_t delivery_mode:3; + uint8_t dest_mode:1; + uint8_t delivery_status:1; + uint8_t polarity:1; + uint8_t remote_irr:1; + uint8_t trig_mode:1; + uint8_t mask:1; + uint8_t reserve:7; + uint8_t reserved[4]; + uint8_t dest_id; + } fields; +}; + #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */ -struct hvm_hw_vioapic { - uint64_t base_address; - uint32_t ioregsel; - uint32_t id; - union vioapic_redir_entry - { - uint64_t bits; - struct { - uint8_t vector; - uint8_t delivery_mode:3; - uint8_t dest_mode:1; - uint8_t delivery_status:1; - uint8_t polarity:1; - uint8_t remote_irr:1; - uint8_t trig_mode:1; - uint8_t mask:1; - uint8_t reserve:7; - uint8_t reserved[4]; - uint8_t dest_id; - } fields; - } redirtbl[VIOAPIC_NUM_PINS]; -}; +#define XEN_HVM_VIOAPIC(name, cnt) \ + struct name { \ + uint64_t base_address; \ + uint32_t ioregsel; \ + uint32_t id; \ + union vioapic_redir_entry redirtbl[cnt]; \ + } + +XEN_HVM_VIOAPIC(hvm_hw_vioapic, VIOAPIC_NUM_PINS); + +#ifndef __XEN__ +#undef XEN_HVM_VIOAPIC +#endif DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);