From patchwork Thu Mar 30 06:19:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9652963 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C6C9C602BD for ; Thu, 30 Mar 2017 06:22:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B5A982856C for ; Thu, 30 Mar 2017 06:22:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A8A8B28571; Thu, 30 Mar 2017 06:22:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A32192856C for ; Thu, 30 Mar 2017 06:22:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctTRV-0000tS-BD; Thu, 30 Mar 2017 06:20:21 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctTRU-0000sX-OO for xen-devel@lists.xen.org; Thu, 30 Mar 2017 06:20:20 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id C7/9A-06437-4A3ACD85; Thu, 30 Mar 2017 06:20:20 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDLMWRWlGSWpSXmKPExsXS1tYhr7tk8Z0 Igy2rmCyWfFzM4sDocXT3b6YAxijWzLyk/IoE1ow7m5+zFzyRr/g/5TZzA+NciS5GTg4hgUqJ LztPMYLYEgK8EkeWzWDtYuQAsv0lbi9172LkAirpZZSYeeoqG0gNm4C+xIrHB1lBbBEBaYlrn y+D9TILVEtMnD4HzBYWsJN4fuwWWD2LgKrE7mu32EFsXgEbid4Pv9khdslLXLh6igXE5hSwlV j9tZ0F4h4bibPXDrFNYORdwMiwilG9OLWoLLVI11IvqSgzPaMkNzEzR9fQwFgvN7W4ODE9NSc xqVgvOT93EyMwFOoZGBh3ML7+6XSIUZKDSUmUd/PcOxFCfEn5KZUZicUZ8UWlOanFhxhlODiU JHh9FgHlBItS01Mr0jJzgEEJk5bg4FES4T0JkuYtLkjMLc5Mh0idYlSUEud1B0kIgCQySvPg2 mCRcIlRVkqYl5GBgUGIpyC1KDezBFX+FaM4B6OSMK8kyBSezLwSuOmvgBYzAS0Wt7kFsrgkES El1cBYrvHtVVl+R0TKgZOO03buu/Q1RGhmhlrfK0e1w3kmWQd8lHV0OPsXrXC6cyxlYnywux2 PqMqHzOfHsg+U3/vG491Y7BP6ZmZY/sSNJTyfjwYfFKx61vP9T1KdtMKSDbLvNllfmMFa+fzm J3G+thUfruolBgnpCMa17phd+neakChfxs+Yc1ZKLMUZiYZazEXFiQCEUinbfwIAAA== X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1490854812!85204125!5 X-Originating-IP: [134.134.136.31] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 25779 invoked from network); 30 Mar 2017 06:20:19 -0000 Received: from mga06.intel.com (HELO mga06.intel.com) (134.134.136.31) by server-16.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 30 Mar 2017 06:20:19 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 29 Mar 2017 23:20:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,245,1486454400"; d="scan'208";a="241919475" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga004.fm.intel.com with ESMTP; 29 Mar 2017 23:20:18 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Thu, 30 Mar 2017 14:19:58 +0800 Message-Id: <20170330062003.9119-5-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170330062003.9119-1-haozhong.zhang@intel.com> References: <20170330062003.9119-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v3 4/9] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest to read/write MSR_IA32_MCG_EXT_CTL. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper Changes in v3: * Replace lmce_enabled in struct hvm_vmce_vcpu and struct vmce by mcg_ext_ctl. * Drop the change to XEN_DOMCTL_INTERFACE_VERSION, as it was changed by c/s 33e5c325 recently. --- xen/arch/x86/cpu/mcheck/vmce.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-x86/mce.h | 1 + xen/include/public/arch-x86/hvm/save.h | 1 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index d591d31..2106706 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -90,6 +90,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt) v->arch.vmce.mcg_cap = ctxt->caps; v->arch.vmce.bank[0].mci_ctl2 = ctxt->mci_ctl2_bank0; v->arch.vmce.bank[1].mci_ctl2 = ctxt->mci_ctl2_bank1; + v->arch.vmce.mcg_ext_ctl = ctxt->mcg_ext_ctl; return 0; } @@ -199,6 +200,26 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_CTL %#"PRIx64"\n", cur, *val); break; + case MSR_IA32_MCG_EXT_CTL: + /* + * If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, the LMCE and LOCK + * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it + * does not need to check them here. + */ + if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + { + *val = cur->arch.vmce.mcg_ext_ctl; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", + cur, *val); + } + else + { + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL, not supported\n", + cur); + } + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0; break; @@ -308,6 +329,16 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) mce_printk(MCE_VERBOSE, "MCE: %pv: MCG_CAP is r/o\n", cur); break; + case MSR_IA32_MCG_EXT_CTL: + if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && + !(val & ~MCG_EXT_CTL_LMCE_EN) ) + cur->arch.vmce.mcg_ext_ctl = val; + else + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: wr MCG_EXT_CTL %"PRIx64"%s\n", + cur, val, (ret == -1) ? ", not supported" : ""); + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_wrmsr(cur, msr, val) : 0; break; @@ -326,7 +357,8 @@ static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h) struct hvm_vmce_vcpu ctxt = { .caps = v->arch.vmce.mcg_cap, .mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2, - .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2 + .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2, + .mcg_ext_ctl = v->arch.vmce.mcg_ext_ctl, }; err = hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt); diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 56ad1f9..35f9962 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -27,6 +27,7 @@ struct vmce_bank { struct vmce { uint64_t mcg_cap; uint64_t mcg_status; + uint64_t mcg_ext_ctl; spinlock_t lock; struct vmce_bank bank[GUEST_MC_BANK_NUM]; }; diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 66ae1a2..ec581cc 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -599,6 +599,7 @@ struct hvm_vmce_vcpu { uint64_t caps; uint64_t mci_ctl2_bank0; uint64_t mci_ctl2_bank1; + uint64_t mcg_ext_ctl; }; DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu);