From patchwork Mon Apr 3 20:28:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9660543 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 54C606032D for ; Mon, 3 Apr 2017 20:28:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 466F328403 for ; Mon, 3 Apr 2017 20:28:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B0682841C; Mon, 3 Apr 2017 20:28:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7BA928403 for ; Mon, 3 Apr 2017 20:28:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cv8Z6-0005dQ-5l; Mon, 03 Apr 2017 20:27:04 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cv8Z4-0005Z4-V7 for xen-devel@lists.xenproject.org; Mon, 03 Apr 2017 20:27:03 +0000 Received: from [85.158.143.35] by server-9.bemta-6.messagelabs.com id 89/C4-03420-610B2E85; Mon, 03 Apr 2017 20:27:02 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTVd0w6M Igx1XlS2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oyZbW2MBR81KubdXMzWwPhNtouRi0NIYCOj xJSJ/SwQznJGiVlnprN2MXJysAnoSuy4+ZoZxBYRCJV4uuA7mM0soCSx/+w1RhBbWMBK4t7TN WBxFgFViSXzbzOB2LwC1hLnb74Bi0sIyEk0nL8PZnMCxVs/HgXrFQLqnfCwiWkCI/cCRoZVjO rFqUVlqUW6RnpJRZnpGSW5iZk5uoYGZnq5qcXFiempOYlJxXrJ+bmbGIH+ZQCCHYzL/jodYpT kYFIS5VWf9ChCiC8pP6UyI7E4I76oNCe1+BCjDAeHkgTvsXVAOcGi1PTUirTMHGCgwaQlOHiU RHg3g6R5iwsSc4sz0yFSpxgVpcR5M0ASAiCJjNI8uDZYcF9ilJUS5mUEOkSIpyC1KDezBFX+F aM4B6OSMO9skCk8mXklcNNfAS1mAlr85M5DkMUliQgpqQZGncDtrRt6lt7UKdgm+dOzVGed5x ariAcd38qMhfbcMdbraZv78/U/84pqG63UaL4ZT4pmyyxSvv9ZbfWvKWuO3fHa81Kq2t+O59h b/vVbjhwK8rs1a6ful5b725ue98ndafq9vFN0RYDjkYoyBfMpiTcdEx57iylNf33n0ILbKz4p Nni/fLTimhJLcUaioRZzUXEiAOlnhtdpAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-13.tower-21.messagelabs.com!1491251220!56020272!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24595 invoked from network); 3 Apr 2017 20:27:01 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-21.messagelabs.com with SMTP; 3 Apr 2017 20:27:01 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B68842B; Mon, 3 Apr 2017 13:27:00 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D5FBE3F4FF; Mon, 3 Apr 2017 13:26:59 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 3 Apr 2017 21:28:29 +0100 Message-Id: <20170403202829.7278-28-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170403202829.7278-1-andre.przywara@arm.com> References: <20170403202829.7278-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v4 27/27] ARM: vGIC: advertise LPI support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP To let a guest know about the availability of virtual LPIs, set the respective bits in the virtual GIC registers and let a guest control the LPI enable bit. Only report the LPI capability if the host has initialized at least one ITS. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 3fc309e..a6a0126 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -168,8 +168,10 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* We have not implemented LPI's, read zero */ - goto read_as_zero_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + *r = vgic_reg32_extract(!!(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED), + info); + return 1; case VREG32(GICR_IIDR): if ( dabt.size != DABT_WORD ) goto bad_width; @@ -181,16 +183,19 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint64_t typer, aff; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - /* TBD: Update processor id in [23:8] when ITS support is added */ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); typer = aff; + typer |= (v->vcpu_id & 0xffff) << 8; if ( v->arch.vgic.flags & VGIC_V3_RDIST_LAST ) typer |= GICR_TYPER_LAST; + if ( v->domain->arch.vgic.has_its ) + typer |= GICR_TYPER_PLPIS; + *r = vgic_reg64_extract(typer, info); return 1; @@ -433,6 +438,35 @@ static uint64_t sanitize_pendbaser(uint64_t reg) return reg; } +static void vgic_vcpu_enable_lpis(struct vcpu *v) +{ + uint64_t reg = v->domain->arch.vgic.rdist_propbase; + unsigned int nr_lpis = BIT((reg & 0x1f) + 1) - LPI_OFFSET; + int nr_pages; + + /* The first VCPU to enable LPIs maps the property table. */ + if ( !v->domain->arch.vgic.nr_lpis ) + { + v->domain->arch.vgic.nr_lpis = nr_lpis; + + nr_pages = DIV_ROUND_UP(nr_lpis, PAGE_SIZE); + get_guest_pages(v->domain, reg & GENMASK_ULL(51, 12), nr_pages); + gprintk(XENLOG_INFO, "VGIC-v3: VCPU%d mapped %d pages for property table\n", + v->vcpu_id, nr_pages); + } + nr_pages = DIV_ROUND_UP(((nr_lpis + LPI_OFFSET) / 8), PAGE_SIZE); + reg = v->arch.vgic.rdist_pendbase; + + get_guest_pages(v->domain, reg & GENMASK_ULL(51, 12), nr_pages); + + gprintk(XENLOG_INFO, "VGIC-v3: VCPU%d mapped %d pages for pending table\n", + v->vcpu_id, nr_pages); + + v->arch.vgic.flags |= VGIC_V3_LPIS_ENABLED; + + printk("VGICv3: enabled %d LPIs for VCPU%d\n", nr_lpis, v->vcpu_id); +} + static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg, register_t r) @@ -443,8 +477,18 @@ static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* LPI's not implemented */ - goto write_ignore_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + if ( !v->domain->arch.vgic.has_its ) + return 1; + + /* LPIs can only be enabled once, but never disabled again. */ + if ( !(r & GICR_CTLR_ENABLE_LPIS) || + (v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED) ) + return 1; + + vgic_vcpu_enable_lpis(v); + + return 1; case VREG32(GICR_IIDR): /* RO */ @@ -1044,6 +1088,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, typer = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | DIV_ROUND_UP(v->domain->arch.vgic.nr_spis, 32)); + if ( v->domain->arch.vgic.has_its ) + { + typer |= GICD_TYPE_LPIS; + irq_bits = 16; + } typer |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; *r = vgic_reg32_extract(typer, info); @@ -1665,6 +1714,21 @@ static int vgic_v3_domain_init(struct domain *d) static void vgic_v3_domain_free(struct domain *d) { + int nr_pages; + struct vcpu *v; + + if ( d->arch.vgic.nr_lpis ) + { + nr_pages = DIV_ROUND_UP(d->arch.vgic.nr_lpis, PAGE_SIZE); + put_guest_pages(d, d->arch.vgic.rdist_propbase & GENMASK_ULL(51, 12), + nr_pages); + + nr_pages = DIV_ROUND_UP((d->arch.vgic.nr_lpis + LPI_OFFSET) / 8, + PAGE_SIZE); + for_each_vcpu(d, v) + put_guest_pages(d, v->arch.vgic.rdist_pendbase & GENMASK_ULL(51, 12), + nr_pages); + } gicv3_its_unmap_all_devices(d); radix_tree_destroy(&d->arch.vgic.pend_lpi_tree, NULL); xfree(d->arch.vgic.rdist_regions);