From patchwork Mon Apr 3 20:28:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9660573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 830D06032D for ; Mon, 3 Apr 2017 20:29:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7364B28403 for ; Mon, 3 Apr 2017 20:29:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6725F2841C; Mon, 3 Apr 2017 20:29:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E486A28403 for ; Mon, 3 Apr 2017 20:29:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cv8Yf-0004uE-T0; Mon, 03 Apr 2017 20:26:37 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cv8Ye-0004tM-7A for xen-devel@lists.xenproject.org; Mon, 03 Apr 2017 20:26:36 +0000 Received: from [193.109.254.147] by server-7.bemta-6.messagelabs.com id 61/00-04817-BFFA2E85; Mon, 03 Apr 2017 20:26:35 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTff3+kc RBov3MFl83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBmXts9lLvinV3F17mS2BsZpKl2MXBxCAhsZ JW63X2aBcJYzSlw98QHI4eRgE9CV2HHzNTOILSIQKvF0wXcwm1lASWL/2WuMILawgK3EvU+/m UBsFgFVie3N7WA1vAJWEnP7DrGD2BICchIN5++DxTkFrCVaPx4F6xUCqpnwsIlpAiP3AkaGVY zqxalFZalFuhZ6SUWZ6RkluYmZObqGBmZ6uanFxYnpqTmJScV6yfm5mxiB/mUAgh2Msy/7H2K U5GBSEuVVn/QoQogvKT+lMiOxOCO+qDQntfgQowwHh5IE77F1QDnBotT01Iq0zBxgoMGkJTh4 lER4N4OkeYsLEnOLM9MhUqcYdTnmzN79hkmIJS8/L1VKnJcfGLZCAiBFGaV5cCNgQX+JUVZKm JcR6CghnoLUotzMElT5V4ziHIxKwrw3QFbxZOaVwG16BXQEE9ART+48BDmiJBEhJdXAKO/+bN OHq9Pf2nPnn59z5729vWaXqUSjO5eE3/msoDt+TDqm2Wc3qOn+W7ss9Nw33aJb39pVVHM2qBi kRC67usXrj3njumRJ5g8RTHVtz+ZKs1dH/jhhZbz3xueamSVihw4XHvrRIcuRLpYW8nS2XW+0 sGlm0bHQxfeVcq8/+1vw88F0bfWvSizFGYmGWsxFxYkA4Tsjg3UCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1491251194!85888546!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23592 invoked from network); 3 Apr 2017 20:26:34 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-27.messagelabs.com with SMTP; 3 Apr 2017 20:26:34 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 34A312B; Mon, 3 Apr 2017 13:26:34 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 70E953F4FF; Mon, 3 Apr 2017 13:26:33 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 3 Apr 2017 21:28:04 +0100 Message-Id: <20170403202829.7278-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170403202829.7278-1-andre.przywara@arm.com> References: <20170403202829.7278-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v4 02/27] ARM: GICv3 ITS: initialize host ITS X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Map the registers frame for each host ITS and populate the host ITS structure with some parameters describing the size of certain properties like the number of bits for device IDs. Introduce a command line parameter to limit the number of devices Xen should handle. This defaults to the value advertised by hardware. Signed-off-by: Andre Przywara --- docs/misc/xen-command-line.markdown | 9 ++++++++ xen/arch/arm/gic-v3-its.c | 38 ++++++++++++++++++++++++++++++++ xen/arch/arm/gic-v3.c | 5 +++++ xen/include/asm-arm/gic_v3_its.h | 44 +++++++++++++++++++++++++++++++++++++ 4 files changed, 96 insertions(+) diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown index 9eb85d6..5a90625 100644 --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -1172,6 +1172,15 @@ based interrupts. Any higher IRQs will be available for use via PCI MSI. ### maxcpus > `= ` +### max\_its\_device\_bits +> `= ` + +Specifies the maximum number of devices using MSIs on the ARM GICv3 ITS +controller to allocate table entries for. Each table entry uses a hardware +specific size, typically 8 or 16 bytes. This value is given as the number +of bits required to hold one device ID. +Defaults to the machine provided value, which is at most 32 bits. + ### mce > `= ` diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 6b02349..58c6ac0 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -19,8 +19,10 @@ */ #include +#include #include #include +#include /* * No lock here, as this list gets only populated upon boot while scanning @@ -33,6 +35,42 @@ bool gicv3_its_host_has_its(void) return !list_empty(&host_its_list); } +/* Allow a user to limit the number of devices. */ +static unsigned int max_its_device_bits = 32; +integer_param("max_its_device_bits", max_its_device_bits); + +static int gicv3_its_init_single_its(struct host_its *hw_its) +{ + uint64_t reg; + + hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size); + if ( !hw_its->its_base ) + return -ENOMEM; + + reg = readq_relaxed(hw_its->its_base + GITS_TYPER); + hw_its->devid_bits = GITS_TYPER_DEVICE_ID_BITS(reg); + hw_its->devid_bits = min(hw_its->devid_bits, max_its_device_bits); + hw_its->evid_bits = GITS_TYPER_EVENT_ID_BITS(reg); + hw_its->itte_size = GITS_TYPER_ITT_SIZE(reg); + + return 0; +} + +int gicv3_its_init(void) +{ + struct host_its *hw_its; + int ret; + + list_for_each_entry(hw_its, &host_its_list, entry) + { + ret = gicv3_its_init_single_its(hw_its); + if ( ret ) + return ret; + } + + return 0; +} + /* Scan the DT for any ITS nodes and create a list of host ITSes out of it. */ void gicv3_its_dt_init(const struct dt_device_node *node) { diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b626298..d3d5784 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1590,6 +1590,11 @@ static int __init gicv3_init(void) spin_lock(&gicv3.lock); gicv3_dist_init(); + + res = gicv3_its_init(); + if ( res ) + panic("GICv3: ITS: initialization failed: %d\n", res); + res = gicv3_cpu_init(); gicv3_hyp_init(); diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index 765a655..7d88987 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -20,6 +20,38 @@ #ifndef __ASM_ARM_ITS_H__ #define __ASM_ARM_ITS_H__ +#define GITS_CTLR 0x000 +#define GITS_IIDR 0x004 +#define GITS_TYPER 0x008 +#define GITS_CBASER 0x080 +#define GITS_CWRITER 0x088 +#define GITS_CREADR 0x090 +#define GITS_BASER_NR_REGS 8 +#define GITS_BASER0 0x100 +#define GITS_BASER1 0x108 +#define GITS_BASER2 0x110 +#define GITS_BASER3 0x118 +#define GITS_BASER4 0x120 +#define GITS_BASER5 0x128 +#define GITS_BASER6 0x130 +#define GITS_BASER7 0x138 + +/* Register bits */ +#define GITS_TYPER_DEVIDS_SHIFT 13 +#define GITS_TYPER_DEVIDS_MASK (0x1fUL << GITS_TYPER_DEVIDS_SHIFT) +#define GITS_TYPER_DEVICE_ID_BITS(r) (((r & GITS_TYPER_DEVIDS_MASK) >> \ + GITS_TYPER_DEVIDS_SHIFT) + 1) + +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_IDBITS_MASK (0x1fUL << GITS_TYPER_IDBITS_SHIFT) +#define GITS_TYPER_EVENT_ID_BITS(r) (((r & GITS_TYPER_IDBITS_MASK) >> \ + GITS_TYPER_IDBITS_SHIFT) + 1) + +#define GITS_TYPER_ITT_SIZE_SHIFT 4 +#define GITS_TYPER_ITT_SIZE_MASK (0xfUL << GITS_TYPER_ITT_SIZE_SHIFT) +#define GITS_TYPER_ITT_SIZE(r) ((((r) & GITS_TYPER_ITT_SIZE_MASK) >> \ + GITS_TYPER_ITT_SIZE_SHIFT) + 1) + #include /* data structure for each hardware ITS */ @@ -28,6 +60,10 @@ struct host_its { const struct dt_device_node *dt_node; paddr_t addr; paddr_t size; + void __iomem *its_base; + unsigned int devid_bits; + unsigned int evid_bits; + unsigned int itte_size; }; @@ -40,6 +76,9 @@ void gicv3_its_dt_init(const struct dt_device_node *node); bool gicv3_its_host_has_its(void); +/* Initialize the host structures for the host ITSes. */ +int gicv3_its_init(void); + #else static LIST_HEAD(host_its_list); @@ -53,6 +92,11 @@ static inline bool gicv3_its_host_has_its(void) return false; } +static inline int gicv3_its_init(void) +{ + return 0; +} + #endif /* CONFIG_HAS_ITS */ #endif