From patchwork Wed Apr 5 19:50:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohit Gambhir X-Patchwork-Id: 9665565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8B0DB60353 for ; Wed, 5 Apr 2017 19:53:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A87328178 for ; Wed, 5 Apr 2017 19:53:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6CE26285A3; Wed, 5 Apr 2017 19:53:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 632CB28178 for ; Wed, 5 Apr 2017 19:53:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvqxW-0008Tp-Hc; Wed, 05 Apr 2017 19:51:14 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvqxV-0008Td-87 for xen-devel@lists.xen.org; Wed, 05 Apr 2017 19:51:13 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id B1/79-03642-0BA45E85; Wed, 05 Apr 2017 19:51:12 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRWlGSWpSXmKPExsUyZ7p8oO4Gr6c RBh9mMlks+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnPzi1iL3gsUnFq6Q+2BsaPAl2MXBxCAhOY JG6962KEcP4wSkz4eZqli5ETyNnAKLF3eylEYjejxJFLm9hBEmwCehKb1ixmB0mICMxmlNi8c jNzFyMHB7OAjsTHhgyQGmGBeIkFx+8zg9gsAqoSU39sARvKK2ArceD9FLC4hICcxKVtX6BsQ4 nPG5cyT2DkWcDIsIpRozi1qCy1SNfQVC+pKDM9oyQ3MTNH19DATC83tbg4MT01JzGpWC85P3c TI9D3DECwg/HbsoBDjJIcTEqivAo+TyKE+JLyUyozEosz4otKc1KLDzHKcHAoSfA+9nwaISRY lJqeWpGWmQMMQpi0BAePkgjvVZA0b3FBYm5xZjpE6hSjopQ4702QhABIIqM0D64NFviXGGWlh HkZgQ4R4ilILcrNLEGVf8UozsGoJMx7H2QKT2ZeCdz0V0CLmYAWP7nzEGRxSSJCSqqBUdLFeu PT2cv5PWYK1TF7V4SnzzpQdGz7klsPoo60bFv3uOfvKQln1hqllzss5G6o3Fzt9efd0VVBkQt sInbuW3G6WHWV0OyEZQYGhTvMRVYp/7hb43O0SpazlyG+stXjjXG6anz9hq6UhjPPLs+rFvw+ U4kz6MMSljOHnii1Tp3cMelKndTZg0osxRmJhlrMRcWJAKREjVJ3AgAA X-Env-Sender: mohit.gambhir@oracle.com X-Msg-Ref: server-15.tower-21.messagelabs.com!1491421870!62282416!1 X-Originating-IP: [156.151.31.81] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTU2LjE1MS4zMS44MSA9PiAyODgzMzk=\n X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 44076 invoked from network); 5 Apr 2017 19:51:11 -0000 Received: from userp1040.oracle.com (HELO userp1040.oracle.com) (156.151.31.81) by server-15.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 5 Apr 2017 19:51:11 -0000 Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id v35Jp79u016380 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 Apr 2017 19:51:07 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id v35Jp6JW013505 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 Apr 2017 19:51:06 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id v35Jp65v029545; Wed, 5 Apr 2017 19:51:06 GMT Received: from dhcp-burlington7-2nd-B-east-10-152-55-229.usdhcp.oraclecorp.com.com (/10.152.55.229) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 05 Apr 2017 12:51:05 -0700 From: Mohit Gambhir To: jun.nakajima@intel.com, kevin.tian@intel.com, boris.ostrovsky@oracle.com, andrew.cooper3@citrix.com, jbeulich@suse.com, xen-devel@lists.xen.org Date: Wed, 5 Apr 2017 15:50:20 -0400 Message-Id: <20170405195020.20701-1-mohit.gambhir@oracle.com> X-Mailer: git-send-email 2.9.3 X-Source-IP: userv0022.oracle.com [156.151.31.74] Cc: Mohit Gambhir Subject: [Xen-devel] [PATCH v2] x86/vpmu_intel: Handle SMT consistently for programmable and fixed counters X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The patch introduces a macro FIXED_CTR_CTRL_ANYTHREAD_MASK and uses it to mask .Anythread bit for all counter in IA32_FIXED_CTR_CTRL MSR in all versions of Intel Arhcitectural Performance Monitoring. Masking .AnyThread bit is necesssry for two reasons: 1. We need to be consistent in the implementation. We disable .Anythread bit in programmable counters (regardless of the version) by masking bit 21 in IA32_PERFEVTSELx. (See code snippet below from vpmu_intel.c) /* Masks used for testing whether and MSR is valid */ #define ARCH_CTRL_MASK (~((1ull << 32) - 1) | (1ull << 21)) But we leave it enabled in fixed function counters for version 3. Removing the condition disables the bit in fixed function counters regardless of the version, which is consistent with what is done for programmable counters. 2. We don't want to expose event counts from another guest (or hypervisor) which can happen if .AnyThread bit is not masked and a VCPU is only scheduled to run on one of the hardware threads in a hyper-threaded CPU. Also, note that Intel SDM discourages the use of .AnyThread bit in virtualized environments (per section 18.2.3.1 AnyThread Counting and Software Evolution). Signed-off-by: Mohit Gambhir Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- xen/arch/x86/cpu/vpmu_intel.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 0d66ecb..3f0322c 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -73,6 +73,7 @@ static bool_t __read_mostly full_width_write; */ #define FIXED_CTR_CTRL_BITS 4 #define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1) +#define FIXED_CTR_CTRL_ANYTHREAD_MASK 0x4 #define ARCH_CNTR_ENABLED (1ULL << 22) @@ -946,6 +947,7 @@ int __init core2_vpmu_init(void) { u64 caps; unsigned int version = 0; + unsigned int i; if ( current_cpu_data.cpuid_level >= 0xa ) version = MASK_EXTR(cpuid_eax(0xa), PMU_VERSION_MASK); @@ -979,8 +981,11 @@ int __init core2_vpmu_init(void) full_width_write = (caps >> 13) & 1; fixed_ctrl_mask = ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1); - if ( version == 2 ) - fixed_ctrl_mask |= 0x444; + /* mask .AnyThread bits for all fixed counters */ + for( i = 0; i < fixed_pmc_cnt; i++ ) + fixed_ctrl_mask |= + (FIXED_CTR_CTRL_ANYTHREAD_MASK << (FIXED_CTR_CTRL_BITS * i)); + fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1); global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1));