From patchwork Fri Apr 7 17:32:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9669985 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5EFF860364 for ; Fri, 7 Apr 2017 17:33:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 517D1262FF for ; Fri, 7 Apr 2017 17:33:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 465DE28497; Fri, 7 Apr 2017 17:33:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B42F6262FF for ; Fri, 7 Apr 2017 17:33:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXjZ-0006F8-GX; Fri, 07 Apr 2017 17:31:41 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXjX-0006BK-Qy for xen-devel@lists.xenproject.org; Fri, 07 Apr 2017 17:31:39 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 27/18-12861-BFCC7E85; Fri, 07 Apr 2017 17:31:39 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTffXmec RBp9+q1p83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBk797SwFGxVqvg26xNzA+MviS5GLg4hgU2M EotmbmOEcJYzShy7so6pi5GTg01AV2LHzdfMILaIQKjEnJ+PwGxmgUqJfx82gdUIC1hJzF/1g g3EZhFQlThxvRsszitgLXHw+0F2EFtCQE6i4fx9sF5OoPjX71vAbCGg3hUbLzJOYORewMiwil GjOLWoLLVI18hSL6koMz2jJDcxM0fX0MBYLze1uDgxPTUnMalYLzk/dxMj0MP1DAyMOxib9vo dYpTkYFIS5VXweRIhxJeUn1KZkVicEV9UmpNafIhRhoNDSYJ30ennEUKCRanpqRVpmTnAUINJ S3DwKInwxoKkeYsLEnOLM9MhUqcYFaXEeRtBEgIgiYzSPLg2WHhfYpSVEuZlZGBgEOIpSC3Kz SxBlX/FKM7BqCTMOwdkCk9mXgnc9FdAi5mAFvvcegqyuCQRISXVwJgxKW6Tzo+yDn71wMcfPg bXJm+9v+XF7zNsU6+W7mieUv1466zIZr9F71aJsNgu217O5xo/dbFu+/rVSR5tvP3ZHxW+Hy7 1MfOpPaFmZLIzht9QZ/2G83/Dbi/29hP7l8g5w5CxO4/pv8ncby+3cRmuy5Cz2un8ebrR1jf5 93e+mn4kNf3pOQ0lluKMREMt5qLiRADtN9HFagIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-2.tower-31.messagelabs.com!1491586297!83136831!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 45351 invoked from network); 7 Apr 2017 17:31:38 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-2.tower-31.messagelabs.com with SMTP; 7 Apr 2017 17:31:38 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD99780D; Fri, 7 Apr 2017 10:31:37 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A95F23F3E1; Fri, 7 Apr 2017 10:31:36 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 7 Apr 2017 18:32:53 +0100 Message-Id: <20170407173307.9788-23-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170407173307.9788-1-andre.przywara@arm.com> References: <20170407173307.9788-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v6 22/36] ARM: vGIC: advertise LPI support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP To let a guest know about the availability of virtual LPIs, set the respective bits in the virtual GIC registers and let a guest control the LPI enable bit. Only report the LPI capability if the host has initialized at least one ITS. This removes a "TBD" comment, as we now populate the processor number in the GICR_TYPE register. Advertise 24 bits worth of LPIs to the guest. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3.c | 59 +++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 7b086b9..1c1d014 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -169,8 +169,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* We have not implemented LPI's, read zero */ - goto read_as_zero_32; + if ( !v->domain->arch.vgic.has_its ) + goto read_as_zero_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + + spin_lock(&v->arch.vgic.lock); + *r = vgic_reg32_extract(!!(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED), + info); + spin_unlock(&v->arch.vgic.lock); + return 1; case VREG32(GICR_IIDR): if ( dabt.size != DABT_WORD ) goto bad_width; @@ -182,16 +189,20 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint64_t typer, aff; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - /* TBD: Update processor id in [23:8] when ITS support is added */ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); typer = aff; + /* We use the VCPU ID as the redistributor ID in bits[23:8] */ + typer |= (v->vcpu_id & 0xffff) << 8; if ( v->arch.vgic.flags & VGIC_V3_RDIST_LAST ) typer |= GICR_TYPER_LAST; + if ( v->domain->arch.vgic.has_its ) + typer |= GICR_TYPER_PLPIS; + *r = vgic_reg64_extract(typer, info); return 1; @@ -421,6 +432,25 @@ static uint64_t sanitize_pendbaser(uint64_t reg) return reg; } +static void vgic_vcpu_enable_lpis(struct vcpu *v) +{ + uint64_t reg = v->domain->arch.vgic.rdist_propbase; + unsigned int nr_lpis = BIT((reg & 0x1f) + 1); + + if ( nr_lpis < LPI_OFFSET ) + nr_lpis = 0; + else + nr_lpis -= LPI_OFFSET; + + if ( !v->domain->arch.vgic.rdists_enabled ) + { + v->domain->arch.vgic.nr_lpis = nr_lpis; + v->domain->arch.vgic.rdists_enabled = true; + } + + v->arch.vgic.flags |= VGIC_V3_LPIS_ENABLED; +} + static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg, register_t r) @@ -431,8 +461,22 @@ static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* LPI's not implemented */ - goto write_ignore_32; + if ( !v->domain->arch.vgic.has_its ) + goto write_ignore_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + + vgic_lock(v); /* protects rdists_enabled */ + spin_lock(&v->arch.vgic.lock); + + /* LPIs can only be enabled once, but never disabled again. */ + if ( (r & GICR_CTLR_ENABLE_LPIS) && + !(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED) ) + vgic_vcpu_enable_lpis(v); + + spin_unlock(&v->arch.vgic.lock); + vgic_unlock(v); + + return 1; case VREG32(GICR_IIDR): /* RO */ @@ -1049,6 +1093,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, typer = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | DIV_ROUND_UP(v->domain->arch.vgic.nr_spis, 32)); + if ( v->domain->arch.vgic.has_its ) + { + typer |= GICD_TYPE_LPIS; + irq_bits = 24; + } typer |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; *r = vgic_reg32_extract(typer, info);