From patchwork Fri Apr 7 17:32:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9670009 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E4D9260364 for ; Fri, 7 Apr 2017 17:33:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D7C47262FF for ; Fri, 7 Apr 2017 17:33:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C90F128446; Fri, 7 Apr 2017 17:33:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5FC012862A for ; Fri, 7 Apr 2017 17:33:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXj9-0005e6-1U; Fri, 07 Apr 2017 17:31:15 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXj8-0005de-BO for xen-devel@lists.xenproject.org; Fri, 07 Apr 2017 17:31:14 +0000 Received: from [85.158.143.35] by server-10.bemta-6.messagelabs.com id 9B/BC-13192-1ECC7E85; Fri, 07 Apr 2017 17:31:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTffhmec RBrOP8Vl83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBlXj5YXNKpXfNzzjrGBca9sFyMXh5DAJkaJ /nMzWCCc5YwSn77vY+ti5ORgE9CV2HHzNTOILSIQKjHn5yMwm1mgUuLfh01MILawgK3Ew+Mzw OIsAqoS8+/NYgWxeQWsJLZM7WAHsSUE5CQazt8Hq+EUsJb4+n0LmC0EVLNi40XGCYzcCxgZVj GqF6cWlaUW6RrqJRVlpmeU5CZm5ugaGpjp5aYWFyemp+YkJhXrJefnbmIEepcBCHYw7nzudIh RkoNJSZRXwedJhBBfUn5KZUZicUZ8UWlOavEhRhkODiUJ3kWnn0cICRalpqdWpGXmAMMMJi3B waMkwjsTJM1bXJCYW5yZDpE6xagoJc7bCJIQAElklObBtcFC+xKjrJQwLyPQIUI8BalFuZklq PKvGMU5GJWEeeeATOHJzCuBm/4KaDET0GKfW09BFpckIqSkGhjFS94pzdpdsDK1PWfrY9Gl8w QDFoeZJVX+NyszUFt/Z+5CzX93tcrqjlTmzt/2P2Dz+U9corw+N2RyMvZVWen5CU4qrnnQOkH HUHeBytStV9LXBkUk8/TqumxuLL9p1aRgs8eC0bJ5z7TNHb/KWJISFERiIvb8XzzhX/DSkwIm jsk3L6yJ0ldiKc5INNRiLipOBACsvojDaAIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1491586272!58292260!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7773 invoked from network); 7 Apr 2017 17:31:12 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-16.tower-21.messagelabs.com with SMTP; 7 Apr 2017 17:31:12 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D36E80D; Fri, 7 Apr 2017 10:31:12 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 586C53F3E1; Fri, 7 Apr 2017 10:31:11 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 7 Apr 2017 18:32:33 +0100 Message-Id: <20170407173307.9788-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170407173307.9788-1-andre.przywara@arm.com> References: <20170407173307.9788-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v6 02/36] ARM: GICv3 ITS: initialize host ITS X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Map the registers frame for each host ITS and populate the host ITS structure with some parameters describing the size of certain properties like the number of bits for device IDs. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v3-its.c | 33 ++++++++++++++++++++++++++++++ xen/arch/arm/gic-v3.c | 5 +++++ xen/include/asm-arm/gic_v3_its.h | 44 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 6b02349..0298866 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -19,8 +19,10 @@ */ #include +#include #include #include +#include /* * No lock here, as this list gets only populated upon boot while scanning @@ -33,6 +35,37 @@ bool gicv3_its_host_has_its(void) return !list_empty(&host_its_list); } +static int gicv3_its_init_single_its(struct host_its *hw_its) +{ + uint64_t reg; + + hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size); + if ( !hw_its->its_base ) + return -ENOMEM; + + reg = readq_relaxed(hw_its->its_base + GITS_TYPER); + hw_its->devid_bits = GITS_TYPER_DEVICE_ID_BITS(reg); + hw_its->evid_bits = GITS_TYPER_EVENT_ID_BITS(reg); + hw_its->itte_size = GITS_TYPER_ITT_SIZE(reg); + + return 0; +} + +int gicv3_its_init(void) +{ + struct host_its *hw_its; + int ret; + + list_for_each_entry(hw_its, &host_its_list, entry) + { + ret = gicv3_its_init_single_its(hw_its); + if ( ret ) + return ret; + } + + return 0; +} + /* Scan the DT for any ITS nodes and create a list of host ITSes out of it. */ void gicv3_its_dt_init(const struct dt_device_node *node) { diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b626298..d3d5784 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1590,6 +1590,11 @@ static int __init gicv3_init(void) spin_lock(&gicv3.lock); gicv3_dist_init(); + + res = gicv3_its_init(); + if ( res ) + panic("GICv3: ITS: initialization failed: %d\n", res); + res = gicv3_cpu_init(); gicv3_hyp_init(); diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index 721e1e2..880904d 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -20,6 +20,38 @@ #ifndef __ASM_ARM_ITS_H__ #define __ASM_ARM_ITS_H__ +#define GITS_CTLR 0x000 +#define GITS_IIDR 0x004 +#define GITS_TYPER 0x008 +#define GITS_CBASER 0x080 +#define GITS_CWRITER 0x088 +#define GITS_CREADR 0x090 +#define GITS_BASER_NR_REGS 8 +#define GITS_BASER0 0x100 +#define GITS_BASER1 0x108 +#define GITS_BASER2 0x110 +#define GITS_BASER3 0x118 +#define GITS_BASER4 0x120 +#define GITS_BASER5 0x128 +#define GITS_BASER6 0x130 +#define GITS_BASER7 0x138 + +/* Register bits */ +#define GITS_TYPER_DEVIDS_SHIFT 13 +#define GITS_TYPER_DEVIDS_MASK (0x1fUL << GITS_TYPER_DEVIDS_SHIFT) +#define GITS_TYPER_DEVICE_ID_BITS(r) (((r & GITS_TYPER_DEVIDS_MASK) >> \ + GITS_TYPER_DEVIDS_SHIFT) + 1) + +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_IDBITS_MASK (0x1fUL << GITS_TYPER_IDBITS_SHIFT) +#define GITS_TYPER_EVENT_ID_BITS(r) (((r & GITS_TYPER_IDBITS_MASK) >> \ + GITS_TYPER_IDBITS_SHIFT) + 1) + +#define GITS_TYPER_ITT_SIZE_SHIFT 4 +#define GITS_TYPER_ITT_SIZE_MASK (0xfUL << GITS_TYPER_ITT_SIZE_SHIFT) +#define GITS_TYPER_ITT_SIZE(r) ((((r) & GITS_TYPER_ITT_SIZE_MASK) >> \ + GITS_TYPER_ITT_SIZE_SHIFT) + 1) + #include /* data structure for each hardware ITS */ @@ -28,6 +60,10 @@ struct host_its { const struct dt_device_node *dt_node; paddr_t addr; paddr_t size; + void __iomem *its_base; + unsigned int devid_bits; + unsigned int evid_bits; + unsigned int itte_size; }; @@ -40,6 +76,9 @@ void gicv3_its_dt_init(const struct dt_device_node *node); bool gicv3_its_host_has_its(void); +/* Initialize the host structures for the host ITSes. */ +int gicv3_its_init(void); + #else static inline void gicv3_its_dt_init(const struct dt_device_node *node) @@ -51,6 +90,11 @@ static inline bool gicv3_its_host_has_its(void) return false; } +static inline int gicv3_its_init(void) +{ + return 0; +} + #endif /* CONFIG_HAS_ITS */ #endif