From patchwork Fri Apr 7 17:32:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9670013 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DA6EC60364 for ; Fri, 7 Apr 2017 17:33:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCFCF28446 for ; Fri, 7 Apr 2017 17:33:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1F18284CE; Fri, 7 Apr 2017 17:33:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6A4DE28628 for ; Fri, 7 Apr 2017 17:33:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXjD-0005fT-JO; Fri, 07 Apr 2017 17:31:19 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cwXjC-0005es-6c for xen-devel@lists.xenproject.org; Fri, 07 Apr 2017 17:31:18 +0000 Received: from [85.158.139.211] by server-12.bemta-5.messagelabs.com id 21/93-31403-5ECC7E85; Fri, 07 Apr 2017 17:31:17 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTffpmec RBseXcFp83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBkHWx+zFsyUq3jfd5algXGBRBcjF4eQwCZG icePP7J2MXICOcsZJVonO4LYbAK6EjtuvmYGsUUEQiXm/HwEZjMLVEr8+7CJCcQWFnCQeLLoG VAvBweLgKrE14s5IGFeASuJ/it7wcolBOQkGs7fB7M5Bawlvn7fwgyxykpixcaLjBMYuRcwMq xi1ChOLSpLLdI1MtNLKspMzyjJTczM0TU0MNXLTS0uTkxPzUlMKtZLzs/dxAj0bj0DA+MOxtu T/Q4xSnIwKYnyKvg8iRDiS8pPqcxILM6ILyrNSS0+xCjDwaEkwbvo9PMIIcGi1PTUirTMHGCY waQlOHiURHhngqR5iwsSc4sz0yFSpxgVpcR5G0ESAiCJjNI8uDZYaF9ilJUS5mVkYGAQ4ilIL crNLEGVf8UozsGoJMw7B2QKT2ZeCdz0V0CLmYAW+9x6CrK4JBEhJdXAWKOTHWmw0lbZoPn2fw uTyCizdqaL6i/s8p6qcOj1HwhhXLl/8an1FTKH8x5cmTv1ybLdy558tzllVP3fU/rKbu6PT63 /rZSyadXpjDdlbf3rkXJCU/kj26XeH6dC3TaV3i29bsw3W7r9TbFBl0fSo76pob4v3r2ZuEz+ pcMlCYkPZq8Y5S4lKbEUZyQaajEXFScCANQ4VPJoAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-3.tower-206.messagelabs.com!1491586276!88868769!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 28864 invoked from network); 7 Apr 2017 17:31:16 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-206.messagelabs.com with SMTP; 7 Apr 2017 17:31:16 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38E3DB16; Fri, 7 Apr 2017 10:31:16 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 281CE3F3E1; Fri, 7 Apr 2017 10:31:15 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 7 Apr 2017 18:32:36 +0100 Message-Id: <20170407173307.9788-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170407173307.9788-1-andre.przywara@arm.com> References: <20170407173307.9788-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v6 05/36] ARM: GICv3 ITS: map ITS command buffer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of directly manipulating the tables in memory, an ITS driver sends commands via a ring buffer in normal system memory to the ITS h/w to create or alter the LPI mappings. Allocate memory for that buffer and tell the ITS about it to be able to send ITS commands. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini Reviewed-by: Julien Grall --- xen/arch/arm/gic-v3-its.c | 53 ++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic_v3_its.h | 6 +++++ 2 files changed, 59 insertions(+) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 27b41ad..3e8d8ce 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -20,10 +20,13 @@ #include #include +#include #include #include #include +#define ITS_CMD_QUEUE_SZ SZ_1M + /* * No lock here, as this list gets only populated upon boot while scanning * firmware tables for all host ITSes, and only gets iterated afterwards. @@ -60,6 +63,51 @@ static uint64_t encode_baser_phys_addr(paddr_t addr, unsigned int page_bits) return ret | ((addr & GENMASK(51, 48)) >> (48 - 12)); } +static void *its_map_cbaser(struct host_its *its) +{ + void __iomem *cbasereg = its->its_base + GITS_CBASER; + uint64_t reg; + void *buffer; + + reg = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; + reg |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; + + buffer = _xzalloc(ITS_CMD_QUEUE_SZ, SZ_64K); + if ( !buffer ) + return NULL; + + if ( virt_to_maddr(buffer) & ~GENMASK(51, 12) ) + { + xfree(buffer); + return NULL; + } + + reg |= GITS_VALID_BIT | virt_to_maddr(buffer); + reg |= ((ITS_CMD_QUEUE_SZ / SZ_4K) - 1) & GITS_CBASER_SIZE_MASK; + writeq_relaxed(reg, cbasereg); + reg = readq_relaxed(cbasereg); + + /* If the ITS dropped shareability, drop cacheability as well. */ + if ( (reg & GITS_BASER_SHAREABILITY_MASK) == 0 ) + { + reg &= ~GITS_BASER_INNER_CACHEABILITY_MASK; + writeq_relaxed(reg, cbasereg); + } + + /* + * If the command queue memory is mapped as uncached, we need to flush + * it on every access. + */ + if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) + { + its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; + printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); + } + + return buffer; +} + /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) @@ -180,6 +228,11 @@ static int gicv3_its_init_single_its(struct host_its *hw_its) } } + hw_its->cmd_buf = its_map_cbaser(hw_its); + if ( !hw_its->cmd_buf ) + return -ENOMEM; + writeq_relaxed(0, hw_its->its_base + GITS_CWRITER); + return 0; } diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index c025622..52f736d 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -79,8 +79,12 @@ #define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) #define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT) +#define GITS_CBASER_SIZE_MASK 0xff + #include +#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) + /* data structure for each hardware ITS */ struct host_its { struct list_head entry; @@ -91,6 +95,8 @@ struct host_its { unsigned int devid_bits; unsigned int evid_bits; unsigned int itte_size; + void *cmd_buf; + unsigned int flags; };