| Message ID | 20170420204008.4745-2-mohit.gambhir@oracle.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 20.04.17 at 22:40, <mohit.gambhir@oracle.com> wrote: > --- a/arch/x86/include/arch/msr-index.h > +++ b/arch/x86/include/arch/msr-index.h > @@ -38,6 +38,17 @@ > #define MSR_GS_BASE 0xc0000101 > #define MSR_SHADOW_GS_BASE 0xc0000102 > > +#define MSR_IA32_PMC(n) (0x000000c1 + (n)) > +#define MSR_IA32_A_PMC(n) (0x000004c1 + (n)) > +#define MSR_IA32_PERFEVTSEL(n) (0x00000186 + (n)) > +#define MSR_IA32_FIXED_CTR(n) (0x00000309 + (n)) > +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038d > +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038f > +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038e > +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 > +#define MSR_IA32_DEBUGCTL 0x000001d9 Imo this should be put in the middle of PMU MSRs. > +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 Overall I also think it would be nice for things to be sorted in some way at least inside this block (perhaps numerically). Jan
On 04/21/2017 02:31 AM, Jan Beulich wrote: >>>> On 20.04.17 at 22:40, <mohit.gambhir@oracle.com> wrote: >> --- a/arch/x86/include/arch/msr-index.h >> +++ b/arch/x86/include/arch/msr-index.h >> @@ -38,6 +38,17 @@ >> #define MSR_GS_BASE 0xc0000101 >> #define MSR_SHADOW_GS_BASE 0xc0000102 >> >> +#define MSR_IA32_PMC(n) (0x000000c1 + (n)) >> +#define MSR_IA32_A_PMC(n) (0x000004c1 + (n)) >> +#define MSR_IA32_PERFEVTSEL(n) (0x00000186 + (n)) >> +#define MSR_IA32_FIXED_CTR(n) (0x00000309 + (n)) >> +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038d >> +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038f >> +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038e >> +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 >> +#define MSR_IA32_DEBUGCTL 0x000001d9 > Imo this should be put in the middle of PMU MSRs. > >> +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 > Overall I also think it would be nice for things to be sorted in > some way at least inside this block (perhaps numerically). Fixed in v2 > Jan > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > https://lists.xen.org/xen-devel
diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h index 2e90079..7df9097 100644 --- a/arch/x86/include/arch/msr-index.h +++ b/arch/x86/include/arch/msr-index.h @@ -38,6 +38,17 @@ #define MSR_GS_BASE 0xc0000101 #define MSR_SHADOW_GS_BASE 0xc0000102 +#define MSR_IA32_PMC(n) (0x000000c1 + (n)) +#define MSR_IA32_A_PMC(n) (0x000004c1 + (n)) +#define MSR_IA32_PERFEVTSEL(n) (0x00000186 + (n)) +#define MSR_IA32_FIXED_CTR(n) (0x00000309 + (n)) +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038d +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038f +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038e +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_IA32_DEBUGCTL 0x000001d9 +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 + #endif /* XFT_X86_MSR_INDEX_H */ /*
This patch adds Intel PMU MSR addresses as macros for VPMU testing Signed-off-by: Mohit Gambhir <mohit.gambhir@oracle.com> --- arch/x86/include/arch/msr-index.h | 11 +++++++++++ 1 file changed, 11 insertions(+)