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Thu, 20 Apr 2017 13:40:38 -0700 From: Mohit Gambhir To: andrew.cooper3@citrix.com, xen-devel@lists.xen.org Date: Thu, 20 Apr 2017 16:40:07 -0400 Message-Id: <20170420204008.4745-2-mohit.gambhir@oracle.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170420204008.4745-1-mohit.gambhir@oracle.com> References: <20170420204008.4745-1-mohit.gambhir@oracle.com> X-Source-IP: userv0021.oracle.com [156.151.31.71] Cc: boris.ostrovsky@oracle.com, Mohit Gambhir Subject: [Xen-devel] [PATCH 1/2][XTF] xtf/vpmu: Add Intel PMU MSR addresses X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Intel PMU MSR addresses as macros for VPMU testing Signed-off-by: Mohit Gambhir --- arch/x86/include/arch/msr-index.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h index 2e90079..7df9097 100644 --- a/arch/x86/include/arch/msr-index.h +++ b/arch/x86/include/arch/msr-index.h @@ -38,6 +38,17 @@ #define MSR_GS_BASE 0xc0000101 #define MSR_SHADOW_GS_BASE 0xc0000102 +#define MSR_IA32_PMC(n) (0x000000c1 + (n)) +#define MSR_IA32_A_PMC(n) (0x000004c1 + (n)) +#define MSR_IA32_PERFEVTSEL(n) (0x00000186 + (n)) +#define MSR_IA32_FIXED_CTR(n) (0x00000309 + (n)) +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038d +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038f +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038e +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_IA32_DEBUGCTL 0x000001d9 +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 + #endif /* XFT_X86_MSR_INDEX_H */ /*