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[RFC,3/4] arm/mem_access: Add further TCR_EL1/TTBCR defines

Message ID 20170430194838.29932-4-proskurin@sec.in.tum.de (mailing list archive)
State New, archived
Headers show

Commit Message

Sergej Proskurin April 30, 2017, 7:48 p.m. UTC 
This commit adds further TCR_EL1/TTBCR defines to simplify access to the
respective register contents.

Signed-off-by: Sergej Proskurin <proskurin@sec.in.tum.de>
---
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Julien Grall <julien.grall@arm.com>
---
 xen/include/asm-arm/processor.h | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Julien Grall May 2, 2017, 12:01 p.m. UTC | #1 
Hi Sergej,

On 30/04/17 20:48, Sergej Proskurin wrote:
> This commit adds further TCR_EL1/TTBCR defines to simplify access to the
> respective register contents.
>
> Signed-off-by: Sergej Proskurin <proskurin@sec.in.tum.de>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Julien Grall <julien.grall@arm.com>
> ---
>  xen/include/asm-arm/processor.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index c8b8cff311..8cf442c73c 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -157,6 +157,8 @@
>  /* TCR: Stage 1 Translation Control */
>
>  #define TCR_T0SZ(x)     ((x)<<0)
> +#define TCR_T0SZ_SHIFT  0
> +#define TCR_T1SZ_SHIFT  16
>
>  #define TCR_IRGN0_NC    (_AC(0x0,UL)<<8)
>  #define TCR_IRGN0_WBWA  (_AC(0x1,UL)<<8)
> @@ -183,6 +185,8 @@
>
>  #define TCR_RES1        (_AC(1,UL)<<31|_AC(1,UL)<<23)
>
> +#define TCR_SZ_MASK     (_AC(0x3f,UL)<<0)
> +

See my comment on patch #2.

>  #else
>
>  #define TCR_RES1        (_AC(1,UL)<<31)
>

Cheers,
diff mbox

Patch

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index c8b8cff311..8cf442c73c 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -157,6 +157,8 @@ 
 /* TCR: Stage 1 Translation Control */
 
 #define TCR_T0SZ(x)     ((x)<<0)
+#define TCR_T0SZ_SHIFT  0
+#define TCR_T1SZ_SHIFT  16
 
 #define TCR_IRGN0_NC    (_AC(0x0,UL)<<8)
 #define TCR_IRGN0_WBWA  (_AC(0x1,UL)<<8)
@@ -183,6 +185,8 @@ 
 
 #define TCR_RES1        (_AC(1,UL)<<31|_AC(1,UL)<<23)
 
+#define TCR_SZ_MASK     (_AC(0x3f,UL)<<0)
+
 #else
 
 #define TCR_RES1        (_AC(1,UL)<<31)