From patchwork Thu May 4 15:31:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9712165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 31A2B6020B for ; Thu, 4 May 2017 15:31:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24192286B6 for ; Thu, 4 May 2017 15:31:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19019286B9; Thu, 4 May 2017 15:31:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E089F286B6 for ; Thu, 4 May 2017 15:31:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Ih3-0004PC-3M; Thu, 04 May 2017 15:29:25 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Ih1-0004Lg-D2 for xen-devel@lists.xenproject.org; Thu, 04 May 2017 15:29:23 +0000 Received: from [85.158.139.211] by server-17.bemta-5.messagelabs.com id F1/36-24726-2D84B095; Thu, 04 May 2017 15:29:22 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTfeSB3e kwa1tHBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8b2SU/ZCs7YVqxabtnAOM2gi5GLQ0hgM6PE mt6zbBDOckaJGcfnsXQxcnKwCehK7Lj5mhnEFhEIlXi64DuYzSygJLH/7DVGEFtYIEhi7ZFrT CA2i4CqxIE/e8B6eQWsJb7NXQcWlxCQk2g4fx+slxMovnfvbjBbSMBK4sOTk2wTGLkXMDKsYt QoTi0qSy3SNbLQSyrKTM8oyU3MzNE1NDDVy00tLk5MT81JTCrWS87P3cQI9G89AwPjDsa+VX6 HGCU5mJREedVfsUcK8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuD97s4dKSRYlJqeWpGWmQMMNJi0 BAePkgjvR5A0b3FBYm5xZjpE6hSjopQ47wqQhABIIqM0D64NFtyXGGWlhHkZGRgYhHgKUotyM 0tQ5V8xinMwKgnzcgFjRYgnM68EbvoroMVMQIubZTlAFpckIqSkGhj574vk8F4Nn/OcR/6Web qncMNH06RQuZM/NnYFfS70vb3rksODc16JnZUej/fWbjbfqhbLsrSnP2lJ2iXthoYC7bbE3S6 HT25/JtaxQcn4z9FbdzfWZojtULDQO2e2uulp+ApjXzM57+W/ph2/53kkf26rX8Gcl3W7LecJ PZL+eFtUUCCsQ16JpTgj0VCLuag4EQCCUSO5aQIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1493911759!76630123!2 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 59666 invoked from network); 4 May 2017 15:29:21 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-206.messagelabs.com with SMTP; 4 May 2017 15:29:21 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 858E515BE; Thu, 4 May 2017 08:29:21 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C4EB33F23B; Thu, 4 May 2017 08:29:20 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 4 May 2017 16:31:23 +0100 Message-Id: <20170504153123.1204-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170504153123.1204-1-andre.przywara@arm.com> References: <20170504153123.1204-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [RFC PATCH 10/10] ARM: vGIC: remove struct irq_rank and support functions X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Now that every information formerly stored in the irq_rank has been transferred over to struct pending_irq, we can get rid of all dead code declaring and initializing the structure and all the support functions. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic.c | 55 -------------------------------------------- xen/include/asm-arm/domain.h | 6 +---- xen/include/asm-arm/vgic.h | 48 -------------------------------------- 3 files changed, 1 insertion(+), 108 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index c7d645e..7680cd8 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -31,35 +31,6 @@ #include #include -static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v, int rank) -{ - if ( rank == 0 ) - return v->arch.vgic.private_irqs; - else if ( rank <= DOMAIN_NR_RANKS(v->domain) ) - return &v->domain->arch.vgic.shared_irqs[rank - 1]; - else - return NULL; -} - -/* - * Returns rank corresponding to a GICD_ register for - * GICD_ with -bits-per-interrupt. - */ -struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, - int s) -{ - int rank = REG_RANK_NR(b, (n >> s)); - - return vgic_get_rank(v, rank); -} - -struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq) -{ - int rank = irq/32; - - return vgic_get_rank(v, rank); -} - static void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq, int vcpu_id) { @@ -70,14 +41,6 @@ static void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq, p->vcpu_id = vcpu_id; } -static void vgic_rank_init(struct vgic_irq_rank *rank, uint8_t index, - unsigned int vcpu) -{ - spin_lock_init(&rank->lock); - - rank->index = index; -} - int domain_vgic_register(struct domain *d, int *mmio_count) { switch ( d->arch.vgic.version ) @@ -116,11 +79,6 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis) spin_lock_init(&d->arch.vgic.lock); - d->arch.vgic.shared_irqs = - xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_RANKS(d)); - if ( d->arch.vgic.shared_irqs == NULL ) - return -ENOMEM; - d->arch.vgic.pending_irqs = xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis); if ( d->arch.vgic.pending_irqs == NULL ) @@ -130,10 +88,6 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis) for (i=0; iarch.vgic.nr_spis; i++) vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i], i + 32, 0); - /* SPIs are routed to VCPU0 by default */ - for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ ) - vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0); - ret = d->arch.vgic.handler->domain_init(d); if ( ret ) return ret; @@ -174,7 +128,6 @@ void domain_vgic_free(struct domain *d) } d->arch.vgic.handler->domain_free(d); - xfree(d->arch.vgic.shared_irqs); xfree(d->arch.vgic.pending_irqs); xfree(d->arch.vgic.allocated_irqs); } @@ -183,13 +136,6 @@ int vcpu_vgic_init(struct vcpu *v) { int i; - v->arch.vgic.private_irqs = xzalloc(struct vgic_irq_rank); - if ( v->arch.vgic.private_irqs == NULL ) - return -ENOMEM; - - /* SGIs/PPIs are always routed to this VCPU */ - vgic_rank_init(v->arch.vgic.private_irqs, 0, v->vcpu_id); - v->domain->arch.vgic.handler->vcpu_init(v); memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs)); @@ -206,7 +152,6 @@ int vcpu_vgic_init(struct vcpu *v) int vcpu_vgic_free(struct vcpu *v) { - xfree(v->arch.vgic.private_irqs); return 0; } diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 6de8082..19531b0 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -83,15 +83,12 @@ struct arch_domain * shared_irqs where each member contains its own locking. * * If both class of lock is required then this lock must be - * taken first. If multiple rank locks are required (including - * the per-vcpu private_irqs rank) then they must be taken in - * rank order. + * taken first. */ spinlock_t lock; uint32_t ctlr; int nr_spis; /* Number of SPIs */ unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ - struct vgic_irq_rank *shared_irqs; /* * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in * struct arch_vcpu. @@ -236,7 +233,6 @@ struct arch_vcpu * struct arch_domain. */ struct pending_irq pending_irqs[32]; - struct vgic_irq_rank *private_irqs; /* This list is ordered by IRQ priority and it is used to keep * track of the IRQs that the VGIC injected into the guest. diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 36e4de2..72095b8 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -96,16 +96,6 @@ struct pending_irq spinlock_t lock; }; -#define NR_INTERRUPT_PER_RANK 32 -#define INTERRUPT_RANK_MASK (NR_INTERRUPT_PER_RANK - 1) - -/* Represents state corresponding to a block of 32 interrupts */ -struct vgic_irq_rank { - spinlock_t lock; /* Covers access to all other members of this struct */ - - uint8_t index; -}; - struct sgi_target { uint8_t aff1; uint16_t list; @@ -130,39 +120,9 @@ struct vgic_ops { const unsigned int max_vcpus; }; -/* Number of ranks of interrupt registers for a domain */ -#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32) - #define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock) #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock) -#define vgic_lock_rank(v, r, flags) spin_lock_irqsave(&(r)->lock, flags) -#define vgic_unlock_rank(v, r, flags) spin_unlock_irqrestore(&(r)->lock, flags) - -/* - * Rank containing GICD_ for GICD_ with - * -bits-per-interrupt - */ -static inline int REG_RANK_NR(int b, uint32_t n) -{ - switch ( b ) - { - /* - * IRQ ranks are of size 32. So n cannot be shifted beyond 5 for 32 - * and above. For 64-bit n is already shifted DBAT_DOUBLE_WORD - * by the caller - */ - case 64: - case 32: return n >> 5; - case 16: return n >> 4; - case 8: return n >> 3; - case 4: return n >> 2; - case 2: return n >> 1; - case 1: return n; - default: BUG(); - } -} - uint32_t gather_irq_info_priority(struct vcpu *v, unsigned int irq); void scatter_irq_info_priority(struct vcpu *v, unsigned int irq, unsigned int value); @@ -283,12 +243,6 @@ VGIC_REG_HELPERS(32, 0x3); enum gic_sgi_mode; -/* - * Offset of GICD_ with its rank, for GICD_ size with - * -bits-per-interrupt. - */ -#define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32) - #define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) extern int domain_vgic_init(struct domain *d, unsigned int nr_spis); @@ -306,8 +260,6 @@ extern void vgic_put_pending_irq(struct domain *d, struct pending_irq *p); extern void vgic_put_pending_irq_unlock(struct domain *d, struct pending_irq *p); extern struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq); -extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s); -extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq); extern bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); extern void vgic_disable_irqs(struct vcpu *v, unsigned int irq, uint32_t r); extern void vgic_enable_irqs(struct vcpu *v, unsigned int irq, uint32_t r);