From patchwork Thu May 4 15:31:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9712159 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 21F3B6020B for ; Thu, 4 May 2017 15:31:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 15A0B286B8 for ; Thu, 4 May 2017 15:31:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0ADBE286BB; Thu, 4 May 2017 15:31:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 97713286B8 for ; Thu, 4 May 2017 15:31:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Igv-0004HB-FB; Thu, 04 May 2017 15:29:17 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Igt-0004GP-Nn for xen-devel@lists.xenproject.org; Thu, 04 May 2017 15:29:15 +0000 Received: from [85.158.137.68] by server-9.bemta-3.messagelabs.com id 8F/CD-01997-BC84B095; Thu, 04 May 2017 15:29:15 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTfeUB3e kQcsJJYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNaP7xEbWgqV8FXPP1jcw3ubuYuTiEBLYyChx 93wLE4SznFHi97UTjF2MnBxsAroSO26+ZgaxRQRCJZ4u+A5mMwsoSew/ew2sRljAX2LjjyNgc RYBVYnLUyFqeAWsJPo3bgCrkRCQk2g4fx8szilgLbF3724wWwio5sOTk2wTGLkXMDKsYtQoTi 0qSy3SNTLXSyrKTM8oyU3MzNE1NDDWy00tLk5MT81JTCrWS87P3cQI9G89AwPjDsaWvX6HGCU 5mJREedVfsUcK8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuCd4c4dKSRYlJqeWpGWmQMMNJi0BAeP kgjvZpA0b3FBYm5xZjpE6hSjopQ47wqQhABIIqM0D64NFtyXGGWlhHkZGRgYhHgKUotyM0tQ5 V8xinMwKgnzBoFM4cnMK4Gb/gpoMRPQ4mZZDpDFJYkIKakGxi1xu9dG/a0q/nDBrMAhoDW1ZD Xj3a3bpqhoCa/a/O3l3e1LZESVdfJ7F9Q4h7wLbbFaw3rodsGNT3qXO1Kvl6yJ+LQ6nbdVwK7 s98mFiqJPui3Nm66d0ypzTj/ZujJt/TRvky+/M4w+3t4uc0rHMHOd4QFFHdadG7h8EmZq1J5v 9rkXG+unq8RSnJFoqMVcVJwIAHyPOM9pAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1493911754!95562352!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7195 invoked from network); 4 May 2017 15:29:14 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 4 May 2017 15:29:14 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C27E32B; Thu, 4 May 2017 08:29:13 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DECC3F23B; Thu, 4 May 2017 08:29:12 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 4 May 2017 16:31:16 +0100 Message-Id: <20170504153123.1204-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170504153123.1204-1-andre.przywara@arm.com> References: <20170504153123.1204-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [RFC PATCH 03/10] ARM: vGIC: introduce and initialize pending_irq lock X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently we protect the pending_irq structure with the corresponding VGIC VCPU lock. For future extensions this leads to problems (for instance if an IRQ is migrating), so let's introduce a per-IRQ lock, which protects the consistency of this structure independent from any VCPU. This patch just introduces and intializes the lock, it is not used anywhere right now. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic.c | 1 + xen/include/asm-arm/vgic.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index f359ecb..f4ae454 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -64,6 +64,7 @@ static void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq) { INIT_LIST_HEAD(&p->inflight); INIT_LIST_HEAD(&p->lr_queue); + spin_lock_init(&p->lock); p->irq = virq; } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 544867a..e7322fc 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -81,6 +81,14 @@ struct pending_irq * TODO: when implementing irq migration, taking only the current * vgic lock is not going to be enough. */ struct list_head lr_queue; + /* The lock protects the consistency of this structure. A single status bit + * can be read and/or set without holding the lock using the atomic + * set_bit/clear_bit/test_bit functions, however accessing multiple bits or + * relating to other members in this struct requires the lock. + * The list_head members are protected by their corresponding VCPU lock, + * it is not sufficient to hold this pending_irq lock here to query or + * change list order or affiliation. */ + spinlock_t lock; }; #define NR_INTERRUPT_PER_RANK 32