From patchwork Thu May 4 15:31:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9712163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3776A6020B for ; Thu, 4 May 2017 15:31:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 287B0286BD for ; Thu, 4 May 2017 15:31:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 16042286BA; Thu, 4 May 2017 15:31:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 675A3286B6 for ; Thu, 4 May 2017 15:31:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Igy-0004J6-27; Thu, 04 May 2017 15:29:20 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d6Igx-0004HP-9L for xen-devel@lists.xenproject.org; Thu, 04 May 2017 15:29:19 +0000 Received: from [193.109.254.147] by server-8.bemta-6.messagelabs.com id 78/7C-03696-FC84B095; Thu, 04 May 2017 15:29:19 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTfecB3e kwaxfYhbft0xmcmD0OPzhCksAYxRrZl5SfkUCa0bbsUa2gk7Pio8rZ7E2MD4362Lk4hAS2MQo sf70bTYIZzmjxPZ3F9m7GDk52AR0JXbcfM0MYosIhEo8XfAdzGYWUJLYf/YaYxcjB4cwUHzaR UWQMIuAqsTai1/AWnkFrCT2XFrGCGJLCMhJNJy/D9bKKWAtsXfvbjBbCKjmw5OTbBMYuRcwMq xi1ChOLSpLLdI1MtRLKspMzyjJTczM0TU0MNPLTS0uTkxPzUlMKtZLzs/dxAj0LwMQ7GD8syz gEKMkB5OSKK/6K/ZIIb6k/JTKjMTijPii0pzU4kOMMhwcShK8M9y5I4UEi1LTUyvSMnOAgQaT luDgURLh3QyS5i0uSMwtzkyHSJ1iVJQS57UGSQiAJDJK8+DaYMF9iVFWSpiXEegQIZ6C1KLcz BJU+VeM4hyMSsK8Z0Gm8GTmlcBNfwW0mAlocbMsB8jikkSElFQD44z37SEXvq6UKWa03fjt90 yNPXOLkg7cTjrzw8Q64IL17M+bdZY7P/l7oyD6VuWpHfarmEKCVosvf37tR3+4AM9nieU/fHa bmobe3cO8ap7SxsSsc4EPu/rUJlim781jNyvL/CYrtmyPMJ+n2al1k1et58/ltKzos7Iprlt4 WfO22Y/nqs2C1UosxRmJhlrMRcWJAKyB4Q9pAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-12.tower-27.messagelabs.com!1493911757!98967374!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 65280 invoked from network); 4 May 2017 15:29:17 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-27.messagelabs.com with SMTP; 4 May 2017 15:29:17 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6FB42344; Thu, 4 May 2017 08:29:17 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 011C73F23B; Thu, 4 May 2017 08:29:15 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 4 May 2017 16:31:19 +0100 Message-Id: <20170504153123.1204-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170504153123.1204-1-andre.przywara@arm.com> References: <20170504153123.1204-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [RFC PATCH 06/10] ARM: vGIC: move config from irq_rank to struct pending_irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently we store the interrupt type configuration (level or edge triggered) in the rank structure. Move this value into struct pending_irq. We just need one bit (edge or level), so use one of the status bits. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v2.c | 29 ++++++++++------------------- xen/arch/arm/vgic-v3.c | 31 ++++++++++++------------------- xen/arch/arm/vgic.c | 39 ++++++++++++++++++++------------------- xen/include/asm-arm/vgic.h | 7 ++++++- 4 files changed, 48 insertions(+), 58 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 5c59fb4..795173c 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -278,20 +278,10 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info, goto read_reserved; case VRANGE32(GICD_ICFGR, GICD_ICFGRN): - { - uint32_t icfgr; - if ( dabt.size != DABT_WORD ) goto bad_width; - rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); - if ( rank == NULL) goto read_as_zero; - vgic_lock_rank(v, rank, flags); - icfgr = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)]; - vgic_unlock_rank(v, rank, flags); - - *r = vgic_reg32_extract(icfgr, info); - + irq = (gicd_reg - GICD_ICFGR) * 4; + *r = vgic_reg32_extract(gather_irq_info_config(v, irq), info); return 1; - } case VRANGE32(0xD00, 0xDFC): goto read_impl_defined; @@ -534,15 +524,16 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info, goto write_ignore_32; case VRANGE32(GICD_ICFGR2, GICD_ICFGRN): /* SPIs */ + { + uint32_t icfgr; + if ( dabt.size != DABT_WORD ) goto bad_width; - rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); - if ( rank == NULL) goto write_ignore; - vgic_lock_rank(v, rank, flags); - vgic_reg32_update(&rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, - DABT_WORD)], - r, info); - vgic_unlock_rank(v, rank, flags); + irq = (gicd_reg - GICD_ICFGR) * 4; + icfgr = gather_irq_info_config(v, irq); + vgic_reg32_update(&icfgr, r, info); + scatter_irq_info_config(v, irq, icfgr); return 1; + } case VRANGE32(0xD00, 0xDFC): goto write_impl_defined; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 10db939..7989989 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -521,20 +521,11 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v, return 1; case VRANGE32(GICD_ICFGR, GICD_ICFGRN): - { - uint32_t icfgr; - if ( dabt.size != DABT_WORD ) goto bad_width; - rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); - if ( rank == NULL ) goto read_as_zero; - vgic_lock_rank(v, rank, flags); - icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)]; - vgic_unlock_rank(v, rank, flags); - - *r = vgic_reg32_extract(icfgr, info); - + irq = (reg - GICD_IPRIORITYR) * 4; + if ( irq >= v->domain->arch.vgic.nr_spis + 32 ) goto read_as_zero; + *r = vgic_reg32_extract(gather_irq_info_config(v, irq), info); return 1; - } default: printk(XENLOG_G_ERR @@ -636,17 +627,19 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v, goto write_ignore_32; case VRANGE32(GICD_ICFGR + 4, GICD_ICFGRN): /* PPI + SPIs */ + { + uint32_t icfgr; + /* ICFGR1 for PPI's, which is implementation defined if ICFGR1 is programmable or not. We chose to program */ if ( dabt.size != DABT_WORD ) goto bad_width; - rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); - if ( rank == NULL ) goto write_ignore; - vgic_lock_rank(v, rank, flags); - vgic_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, - DABT_WORD)], - r, info); - vgic_unlock_rank(v, rank, flags); + irq = (reg - GICD_ICFGR) * 4; + if ( irq >= v->domain->arch.vgic.nr_spis + 32 ) goto write_ignore; + icfgr = gather_irq_info_config(v, irq); + vgic_reg32_update(&icfgr, r, info); + scatter_irq_info_config(v, irq, icfgr); return 1; + } default: printk(XENLOG_G_ERR diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 68eef47..02c1d12 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -235,6 +235,19 @@ static void set_priority(struct pending_irq *p, uint8_t prio) p->new_priority = prio; } +unsigned int extract_config(struct pending_irq *p) +{ + return test_bit(GIC_IRQ_GUEST_EDGE, &p->status) ? 2 : 0; +} + +static void set_config(struct pending_irq *p, unsigned int config) +{ + if ( config < 2 ) + clear_bit(GIC_IRQ_GUEST_EDGE, &p->status); + else + set_bit(GIC_IRQ_GUEST_EDGE, &p->status); +} + #define DEFINE_GATHER_IRQ_INFO(name, get_val, shift) \ uint32_t gather_irq_info_##name(struct vcpu *v, unsigned int irq) \ @@ -267,6 +280,8 @@ void scatter_irq_info_##name(struct vcpu *v, unsigned int irq, \ /* grep fodder: gather_irq_info_priority, scatter_irq_info_priority below */ DEFINE_GATHER_IRQ_INFO(priority, extract_priority, 8) DEFINE_SCATTER_IRQ_INFO(priority, set_priority, 8) +DEFINE_GATHER_IRQ_INFO(config, extract_config, 2) +DEFINE_SCATTER_IRQ_INFO(config, set_config, 2) bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) { @@ -357,27 +372,11 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) } } -#define VGIC_ICFG_MASK(intr) (1 << ((2 * ((intr) % 16)) + 1)) - -/* The function should be called with the rank lock taken */ -static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index) -{ - struct vgic_irq_rank *r = vgic_get_rank(v, n); - uint32_t tr = r->icfg[index >> 4]; - - ASSERT(spin_is_locked(&r->lock)); - - if ( tr & VGIC_ICFG_MASK(index) ) - return IRQ_TYPE_EDGE_RISING; - else - return IRQ_TYPE_LEVEL_HIGH; -} - void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) { const unsigned long mask = r; struct pending_irq *p; - unsigned int irq; + unsigned int irq, int_type; unsigned long flags; int i = 0; struct vcpu *v_target; @@ -392,6 +391,8 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) spin_lock(&p->lock); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + int_type = test_bit(GIC_IRQ_GUEST_EDGE, &p->status) ? + IRQ_TYPE_EDGE_RISING : IRQ_TYPE_LEVEL_HIGH; if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) gic_raise_guest_irq(v_target, p); @@ -399,15 +400,15 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) spin_unlock_irqrestore(&v_target->arch.vgic.lock, flags); if ( p->desc != NULL ) { - irq_set_affinity(p->desc, cpumask_of(v_target->processor)); spin_lock_irqsave(&p->desc->lock, flags); + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); /* * The irq cannot be a PPI, we only support delivery of SPIs * to guests. */ ASSERT(irq >= 32); if ( irq_type_set_by_domain(d) ) - gic_set_irq_type(p->desc, vgic_get_virq_type(v, n, i)); + gic_set_irq_type(p->desc, int_type); p->desc->handler->enable(p->desc); spin_unlock_irqrestore(&p->desc->lock, flags); } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 38a5e76..931a672 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -60,12 +60,15 @@ struct pending_irq * vcpu while it is still inflight and on an GICH_LR register on the * old vcpu. * + * GIC_IRQ_GUEST_EDGE: the IRQ is an edge triggered interrupt. + * */ #define GIC_IRQ_GUEST_QUEUED 0 #define GIC_IRQ_GUEST_ACTIVE 1 #define GIC_IRQ_GUEST_VISIBLE 2 #define GIC_IRQ_GUEST_ENABLED 3 #define GIC_IRQ_GUEST_MIGRATING 4 +#define GIC_IRQ_GUEST_EDGE 5 unsigned long status; struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */ unsigned int irq; @@ -102,7 +105,6 @@ struct vgic_irq_rank { uint8_t index; uint32_t ienable; - uint32_t icfg[2]; /* * It's more convenient to store a target VCPU per vIRQ @@ -173,6 +175,9 @@ static inline int REG_RANK_NR(int b, uint32_t n) uint32_t gather_irq_info_priority(struct vcpu *v, unsigned int irq); void scatter_irq_info_priority(struct vcpu *v, unsigned int irq, unsigned int value); +uint32_t gather_irq_info_config(struct vcpu *v, unsigned int irq); +void scatter_irq_info_config(struct vcpu *v, unsigned int irq, + unsigned int value); #define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8)))