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Thu, 04 May 2017 14:33:38 -0700 From: Mohit Gambhir To: andrew.cooper3@citrix.com, xen-devel@lists.xen.org Date: Thu, 4 May 2017 17:32:59 -0400 Message-Id: <20170504213300.5661-2-mohit.gambhir@oracle.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170504213300.5661-1-mohit.gambhir@oracle.com> References: <20170504213300.5661-1-mohit.gambhir@oracle.com> X-Source-IP: userv0022.oracle.com [156.151.31.74] Cc: boris.ostrovsky@oracle.com, mgambhir@outlook.com, Mohit Gambhir Subject: [Xen-devel] [PATCH v5 1/2] xtf/vpmu: Add Intel PMU MSR addresses X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Intel PMU MSR addresses as macros for VPMU testing Signed-off-by: Mohit Gambhir --- arch/x86/include/arch/msr-index.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h index 72373c6..911d7f9 100644 --- a/arch/x86/include/arch/msr-index.h +++ b/arch/x86/include/arch/msr-index.h @@ -3,6 +3,8 @@ #include +#define MSR_PMC(n) (0x000000c1 + (n)) + #define MSR_INTEL_PLATFORM_INFO 0x000000ce #define _MSR_PLATFORM_INFO_CPUID_FAULTING 31 #define MSR_PLATFORM_INFO_CPUID_FAULTING (1ULL << _MSR_PLATFORM_INFO_CPUID_FAULTING) @@ -11,10 +13,20 @@ #define _MSR_MISC_FEATURES_CPUID_FAULTING 0 #define MSR_MISC_FEATURES_CPUID_FAULTING (1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING) +#define MSR_PERFEVTSEL(n) (0x00000186 + (n)) + #define MSR_DEBUGCTL 0x000001d9 #define _MSR_DEBUGCTL_LBR 0 /* Last Branch Record. */ #define MSR_DEBUGCTL_LBR (_AC(1, L) << _MSR_DEBUGCTL_LBR) +#define MSR_FIXED_CTR(n) (0x00000309 + (n)) +#define MSR_PERF_CAPABILITIES 0x00000345 +#define MSR_FIXED_CTR_CTRL 0x0000038d +#define MSR_PERF_GLOBAL_STATUS 0x0000038e +#define MSR_PERF_GLOBAL_CTRL 0x0000038f +#define MSR_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_A_PMC(n) (0x000004c1 + (n)) + #define MSR_EFER 0xc0000080 /* Extended Feature register. */ #define _EFER_SCE 0 /* SYSCALL Enable. */ #define EFER_SCE (_AC(1, L) << _EFER_SCE)