From patchwork Thu May 11 17:53:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9722629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A089D6031B for ; Thu, 11 May 2017 17:53:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A0167286D0 for ; Thu, 11 May 2017 17:53:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 94F8E286E5; Thu, 11 May 2017 17:53:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 036C2286D0 for ; Thu, 11 May 2017 17:53:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFc-0000WW-S3; Thu, 11 May 2017 17:51:44 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFb-0000RY-Cp for xen-devel@lists.xenproject.org; Thu, 11 May 2017 17:51:43 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id C2/2B-02005-FA4A4195; Thu, 11 May 2017 17:51:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRWlGSWpSXmKPExsVysyfVTXfdEpF Ig/Z1Yhbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bs42tZCp6pVBzuPMnYwPhCqouRi0NIYDOj xPTWcywQznJGiXffnrF3MXJysAnoSuy4+ZoZxBYRCJV4uuA7M0gRs8AaRolzi36ygSSEBawkD t99BdbAIqAq0X7uEQuIzStgLTHjdgNYXEJATqLh/H2wQZxA8SXTZ4HVCAH17tp9mnUCI/cCRo ZVjBrFqUVlqUW6RhZ6SUWZ6RkluYmZObqGBsZ6uanFxYnpqTmJScV6yfm5mxiBPq5nYGDcwdh +wu8QoyQHk5IoL+NEkUghvqT8lMqMxOKM+KLSnNTiQ4wyHBxKEryRi4FygkWp6akVaZk5wGCD SUtw8CiJ8G5eBJTmLS5IzC3OTIdInWJUlBLn5QHpEwBJZJTmwbXBAvwSo6yUMC8jAwODEE9Ba lFuZgmq/CtGcQ5GJWFeO5ApPJl5JXDTXwEtZgJa3P9HGGRxSSJCSqqB8aAyg/GDbLZsz8Yr9m v6HryZl3R/8rqiPS+7oo3C20IPFq6XL2iYesviRNRMk/83Ije/3r/l4PzCgymXbRPrF+l+Ocj KUSRy4cp+tR/T18heWptk4XpZMsG/Wynm1QrTPbzPGf9lnHXKljgY9FxjLd/2E/9ZQz4w/Vuv ksDPs9rF6ip/RZ3qFCWW4oxEQy3mouJEAMERMgdrAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-13.tower-31.messagelabs.com!1494525101!99387017!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 13462 invoked from network); 11 May 2017 17:51:42 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-31.messagelabs.com with SMTP; 11 May 2017 17:51:42 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69F201991; Thu, 11 May 2017 10:51:41 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 433AB3F4FF; Thu, 11 May 2017 10:51:40 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 11 May 2017 18:53:24 +0100 Message-Id: <20170511175340.8448-13-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170511175340.8448-1-andre.przywara@arm.com> References: <20170511175340.8448-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v9 12/28] ARM: vGIC: advertise LPI support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP To let a guest know about the availability of virtual LPIs, set the respective bits in the virtual GIC registers and let a guest control the LPI enable bit. Only report the LPI capability if the host has initialized at least one ITS. This removes a "TBD" comment, as we now populate the processor number in the GICR_TYPE register. Advertise 24 bits worth of LPIs to the guest. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 38c123c..6dbdb2e 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -170,8 +170,19 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* We have not implemented LPI's, read zero */ - goto read_as_zero_32; + { + unsigned long flags; + + if ( !v->domain->arch.vgic.has_its ) + goto read_as_zero_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + *r = vgic_reg32_extract(!!(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED), + info); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + return 1; + } case VREG32(GICR_IIDR): if ( dabt.size != DABT_WORD ) goto bad_width; @@ -183,16 +194,20 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint64_t typer, aff; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - /* TBD: Update processor id in [23:8] when ITS support is added */ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); typer = aff; + /* We use the VCPU ID as the redistributor ID in bits[23:8] */ + typer |= (v->vcpu_id & 0xffff) << 8; if ( v->arch.vgic.flags & VGIC_V3_RDIST_LAST ) typer |= GICR_TYPER_LAST; + if ( v->domain->arch.vgic.has_its ) + typer |= GICR_TYPER_PLPIS; + *r = vgic_reg64_extract(typer, info); return 1; @@ -426,6 +441,28 @@ static uint64_t sanitize_pendbaser(uint64_t reg) return reg; } +static void vgic_vcpu_enable_lpis(struct vcpu *v) +{ + uint64_t reg = v->domain->arch.vgic.rdist_propbase; + unsigned int nr_lpis = BIT((reg & 0x1f) + 1); + + /* rdists_enabled is protected by the domain lock. */ + ASSERT(spin_is_locked(&v->domain->arch.vgic.lock)); + + if ( nr_lpis < LPI_OFFSET ) + nr_lpis = 0; + else + nr_lpis -= LPI_OFFSET; + + if ( !v->domain->arch.vgic.rdists_enabled ) + { + v->domain->arch.vgic.nr_lpis = nr_lpis; + v->domain->arch.vgic.rdists_enabled = true; + } + + v->arch.vgic.flags |= VGIC_V3_LPIS_ENABLED; +} + static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg, register_t r) @@ -436,8 +473,26 @@ static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info, switch ( gicr_reg ) { case VREG32(GICR_CTLR): - /* LPI's not implemented */ - goto write_ignore_32; + { + unsigned long flags; + + if ( !v->domain->arch.vgic.has_its ) + goto write_ignore_32; + if ( dabt.size != DABT_WORD ) goto bad_width; + + vgic_lock(v); /* protects rdists_enabled */ + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + /* LPIs can only be enabled once, but never disabled again. */ + if ( (r & GICR_CTLR_ENABLE_LPIS) && + !(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED) ) + vgic_vcpu_enable_lpis(v); + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + vgic_unlock(v); + + return 1; + } case VREG32(GICR_IIDR): /* RO */ @@ -1058,6 +1113,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, typer = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | DIV_ROUND_UP(v->domain->arch.vgic.nr_spis, 32)); + if ( v->domain->arch.vgic.has_its ) + { + typer |= GICD_TYPE_LPIS; + irq_bits = v->domain->arch.vgic.intid_bits; + } typer |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; *r = vgic_reg32_extract(typer, info);