From patchwork Thu May 11 17:53:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9722679 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A37D960236 for ; Thu, 11 May 2017 17:54:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A3864286D9 for ; Thu, 11 May 2017 17:54:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9861A286E6; Thu, 11 May 2017 17:54:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0B699286D9 for ; Thu, 11 May 2017 17:54:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFg-0000cJ-Er; Thu, 11 May 2017 17:51:48 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFe-0000Yh-Lr for xen-devel@lists.xenproject.org; Thu, 11 May 2017 17:51:46 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 7D/81-27980-1B4A4195; Thu, 11 May 2017 17:51:45 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTXfjEpF IgyMTuS2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oz2zgusBXPNK9Zu+8zawHhXs4uRi0NIYDOj xPzVj1ghnOWMEgsmn2TrYuTkYBPQldhx8zUziC0iECrxdMF3ZpAiZoE1jBLnFv0EKxIWcJOY2 /SZvYuRg4NFQFXiXwM/SJhXwFpiV8cqVhBbQkBOouH8fbA5nEDxJdNnsYDYQgJWErt2n2adwM i9gJFhFaN6cWpRWWqRrqFeUlFmekZJbmJmjq6hgbFebmpxcWJ6ak5iUrFecn7uJkagfxmAYAf j8o9OhxglOZiURHkZJ4pECvEl5adUZiQWZ8QXleakFh9ilOHgUJLgvboYKCdYlJqeWpGWmQMM NJi0BAePkgjvEpA0b3FBYm5xZjpE6hSjopQ4bztIQgAkkVGaB9cGC+5LjLJSwryMQIcI8RSkF uVmlqDKv2IU52BUEua1A5nCk5lXAjf9FdBiJqDF/X+EQRaXJCKkpBoYD/GsYFmuWWag9/Gl9c uT55UyZ6y2fhha3RDc1PRROCZ7vtbNDwtq3cufqSxPi9Jo8zdryYuqYu3oyTLe/tLpxXGBI2d lVdXexInfZds+cXkplyzPlu5YR48jYRtzkpnVKo5diM88MI89TPbJmoMKZY3hJWU1jy66cxnf e/wph/XCNKW7uc5KLMUZiYZazEXFiQDK9bVNaQIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1494525104!96792826!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8080 invoked from network); 11 May 2017 17:51:44 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 11 May 2017 17:51:44 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D39B19CC; Thu, 11 May 2017 10:51:44 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 160C03F4FF; Thu, 11 May 2017 10:51:42 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 11 May 2017 18:53:26 +0100 Message-Id: <20170511175340.8448-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170511175340.8448-1-andre.przywara@arm.com> References: <20170511175340.8448-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v9 14/28] ARM: vITS: introduce translation table walks X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The ITS stores the target (v)CPU and the (virtual) LPI number in tables. Introduce functions to walk those tables and translate an device ID - event ID pair into a pair of virtual LPI and vCPU. We map those tables on demand - which is cheap on arm64 - and copy the respective entries before using them, to avoid the guest tampering with them meanwhile. To allow compiling without warnings, we declare two functions as non-static for the moment, which two later patches will fix. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3-its.c | 183 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index e3bd1f6..12ec5f1 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -81,6 +81,7 @@ struct vits_itte typedef uint16_t coll_table_entry_t; typedef uint64_t dev_table_entry_t; +#define UNMAPPED_COLLECTION ((coll_table_entry_t)~0) #define GITS_BASER_RO_MASK (GITS_BASER_TYPE_MASK | \ (31UL << GITS_BASER_ENTRY_SIZE_SHIFT)) @@ -97,6 +98,188 @@ void vgic_v3_its_free_domain(struct domain *d) ASSERT(RB_EMPTY_ROOT(&d->arch.vgic.its_devices)); } +/* + * The physical address is encoded slightly differently depending on + * the used page size: the highest four bits are stored in the lowest + * four bits of the field for 64K pages. + */ +static paddr_t get_baser_phys_addr(uint64_t reg) +{ + if ( reg & BIT(9) ) + return (reg & GENMASK(47, 16)) | + ((reg & GENMASK(15, 12)) << 36); + else + return reg & GENMASK(47, 12); +} + +/* + * Our collection table encoding: + * Just contains the 16-bit VCPU ID of the respective vCPU. + */ + +/* Must be called with the ITS lock held. */ +static struct vcpu *get_vcpu_from_collection(struct virt_its *its, + uint16_t collid) +{ + paddr_t addr = get_baser_phys_addr(its->baser_coll); + coll_table_entry_t vcpu_id; + int ret; + + ASSERT(spin_is_locked(&its->its_lock)); + + if ( collid >= its->max_collections ) + return NULL; + + ret = vgic_access_guest_memory(its->d, + addr + collid * sizeof(coll_table_entry_t), + &vcpu_id, sizeof(vcpu_id), false); + if ( ret ) + return NULL; + + if ( vcpu_id == UNMAPPED_COLLECTION || vcpu_id >= its->d->max_vcpus ) + return NULL; + + return its->d->vcpu[vcpu_id]; +} + +/* + * Our device table encodings: + * Contains the guest physical address of the Interrupt Translation Table in + * bits [51:8], and the size of it is encoded as the number of bits minus one + * in the lowest 5 bits of the word. + */ +#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK(51, 8)) +#define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(4, 0)) + 1)) +#define DEV_TABLE_ENTRY(addr, bits) \ + (((addr) & GENMASK(51, 8)) | (((bits) - 1) & GENMASK(4, 0))) + +/* + * Lookup the address of the Interrupt Translation Table associated with + * that device ID. + * TODO: add support for walking indirect tables. + */ +static int its_get_itt(struct virt_its *its, uint32_t devid, + dev_table_entry_t *itt) +{ + paddr_t addr = get_baser_phys_addr(its->baser_dev); + + if ( devid >= its->max_devices ) + return -EINVAL; + + return vgic_access_guest_memory(its->d, + addr + devid * sizeof(dev_table_entry_t), + itt, sizeof(*itt), false); +} + +/* + * Lookup the address of the Interrupt Translation Table associated with + * a device ID and return the address of the ITTE belonging to the event ID + * (which is an index into that table). + */ +static paddr_t its_get_itte_address(struct virt_its *its, + uint32_t devid, uint32_t evid) +{ + dev_table_entry_t itt; + int ret; + + ret = its_get_itt(its, devid, &itt); + if ( ret ) + return INVALID_PADDR; + + if ( evid >= DEV_TABLE_ITT_SIZE(itt) || + DEV_TABLE_ITT_ADDR(itt) == INVALID_PADDR ) + return INVALID_PADDR; + + return DEV_TABLE_ITT_ADDR(itt) + evid * sizeof(struct vits_itte); +} + +/* + * Queries the collection and device tables to get the vCPU and virtual + * LPI number for a given guest event. This first accesses the guest memory + * to resolve the address of the ITTE, then reads the ITTE entry at this + * address and puts the result in vcpu_ptr and vlpi_ptr. + * Must be called with the ITS lock held. + */ +static bool read_itte_locked(struct virt_its *its, uint32_t devid, + uint32_t evid, struct vcpu **vcpu_ptr, + uint32_t *vlpi_ptr) +{ + paddr_t addr; + struct vits_itte itte; + struct vcpu *vcpu; + + ASSERT(spin_is_locked(&its->its_lock)); + + addr = its_get_itte_address(its, devid, evid); + if ( addr == INVALID_PADDR ) + return false; + + if ( vgic_access_guest_memory(its->d, addr, &itte, sizeof(itte), false) ) + return false; + + vcpu = get_vcpu_from_collection(its, itte.collection); + if ( !vcpu ) + return false; + + *vcpu_ptr = vcpu; + *vlpi_ptr = itte.vlpi; + return true; +} + +/* + * This function takes care of the locking by taking the its_lock itself, so + * a caller shall not hold this. Before returning, the lock is dropped again. + */ +bool read_itte(struct virt_its *its, uint32_t devid, uint32_t evid, + struct vcpu **vcpu_ptr, uint32_t *vlpi_ptr) +{ + bool ret; + + spin_lock(&its->its_lock); + ret = read_itte_locked(its, devid, evid, vcpu_ptr, vlpi_ptr); + spin_unlock(&its->its_lock); + + return ret; +} + +/* + * Queries the collection and device tables to translate the device ID and + * event ID and find the appropriate ITTE. The given collection ID and the + * virtual LPI number are then stored into that entry. + * If vcpu_ptr is provided, returns the VCPU belonging to that collection. + * Must be called with the ITS lock held. + */ +bool write_itte_locked(struct virt_its *its, uint32_t devid, + uint32_t evid, uint32_t collid, uint32_t vlpi, + struct vcpu **vcpu_ptr) +{ + paddr_t addr; + struct vits_itte itte; + + ASSERT(spin_is_locked(&its->its_lock)); + + if ( collid >= its->max_collections ) + return false; + + if ( vlpi >= its->d->arch.vgic.nr_lpis ) + return false; + + addr = its_get_itte_address(its, devid, evid); + if ( addr == INVALID_PADDR ) + return false; + + itte.collection = collid; + itte.vlpi = vlpi; + + if ( vgic_access_guest_memory(its->d, addr, &itte, sizeof(itte), true) ) + return false; + + if ( vcpu_ptr ) + *vcpu_ptr = get_vcpu_from_collection(its, collid); + + return true; +} + /************************************** * Functions that handle ITS commands * **************************************/