@@ -1579,6 +1579,7 @@ static int __init gicv3_init(void)
{
int res, i;
uint32_t reg;
+ unsigned int intid_bits;
if ( !cpu_has_gicv3 )
{
@@ -1622,8 +1623,11 @@ static int __init gicv3_init(void)
i, r->base, r->base + r->size);
}
+ reg = readl_relaxed(GICD + GICD_TYPER);
+ intid_bits = GICD_TYPE_ID_BITS(reg);
+
vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions,
- gicv3.rdist_stride);
+ gicv3.rdist_stride, intid_bits);
gicv3_init_v2();
spin_lock_init(&gicv3.lock);
@@ -57,18 +57,21 @@ static struct {
unsigned int nr_rdist_regions;
const struct rdist_region *regions;
uint32_t rdist_stride; /* Re-distributor stride */
+ unsigned int intid_bits; /* Number of interrupt ID bits */
} vgic_v3_hw;
void vgic_v3_setup_hw(paddr_t dbase,
unsigned int nr_rdist_regions,
const struct rdist_region *regions,
- uint32_t rdist_stride)
+ uint32_t rdist_stride,
+ unsigned int intid_bits)
{
vgic_v3_hw.enabled = 1;
vgic_v3_hw.dbase = dbase;
vgic_v3_hw.nr_rdist_regions = nr_rdist_regions;
vgic_v3_hw.regions = regions;
vgic_v3_hw.rdist_stride = rdist_stride;
+ vgic_v3_hw.intid_bits = intid_bits;
}
static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter)
@@ -1482,6 +1485,8 @@ static int vgic_v3_domain_init(struct domain *d)
first_cpu += size / d->arch.vgic.rdist_stride;
}
+
+ d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits;
}
else
{
@@ -1497,6 +1502,8 @@ static int vgic_v3_domain_init(struct domain *d)
d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE;
d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE;
d->arch.vgic.rdist_regions[0].first_cpu = 0;
+
+ d->arch.vgic.intid_bits = GUEST_GICV3_GICD_INTID_BITS;
}
ret = vgic_v3_its_init_domain(d);
@@ -111,6 +111,7 @@ struct arch_domain
uint32_t rdist_stride; /* Re-Distributor stride */
struct rb_root its_devices; /* Devices mapped to an ITS */
spinlock_t its_devices_lock; /* Protects the its_devices tree */
+ unsigned int intid_bits;
#endif
} vgic;
@@ -346,7 +346,8 @@ struct rdist_region;
void vgic_v3_setup_hw(paddr_t dbase,
unsigned int nr_rdist_regions,
const struct rdist_region *regions,
- uint32_t rdist_stride);
+ uint32_t rdist_stride,
+ unsigned int intid_bits);
#endif
#endif /* __ASM_ARM_VGIC_H__ */
@@ -400,6 +400,10 @@ typedef uint64_t xen_callback_t;
#define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000)
#define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000)
+/* TODO: Should this number be a tool stack decision? */
+/* The number of interrupt ID bits a guest (not Dom0) sees. */
+#define GUEST_GICV3_GICD_INTID_BITS 16
+
#define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000)
#define GUEST_GICV3_RDIST_REGIONS 1
The host supports a certain number of LPI identifiers, as stored in the GICD_TYPER register. Store this number from the hardware register in vgic_v3_hw to allow injecting the very same number into a guest (Dom0). DomUs get a fixed limited number for now. We may want to revisit this when we get proper DomU ITS support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- xen/arch/arm/gic-v3.c | 6 +++++- xen/arch/arm/vgic-v3.c | 9 ++++++++- xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/vgic.h | 3 ++- xen/include/public/arch-arm.h | 4 ++++ 5 files changed, 20 insertions(+), 3 deletions(-)