From patchwork Thu May 11 17:53:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9722637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5026B6031B for ; Thu, 11 May 2017 17:53:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F0F8286D0 for ; Thu, 11 May 2017 17:53:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41385286E5; Thu, 11 May 2017 17:53:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B2429286D0 for ; Thu, 11 May 2017 17:53:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFn-0000nm-0P; Thu, 11 May 2017 17:51:55 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFm-0000ju-Ec for xen-devel@lists.xenproject.org; Thu, 11 May 2017 17:51:54 +0000 Received: from [193.109.254.147] by server-5.bemta-6.messagelabs.com id 72/25-03371-AB4A4195; Thu, 11 May 2017 17:51:54 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTXfnEpF Ig23bZS2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oxtj3cxFSzSrmhY28TawLhPsYuRi0NIYDOj xPFVh5khnOWMEit+32bqYuTkYBPQldhx8zUziC0iECrxdMF3sCJmgTWMEucW/WQDSQgLWEk0r lvC2sXIwcEioCqx7lwKSJhXwFpi16LvYHMkBOQkGs7fB5vDCRRfMn0WC4gtBNS6a/dp1gmM3A sYGVYxqhenFpWlFuma6yUVZaZnlOQmZuboGhqY6eWmFhcnpqfmJCYV6yXn525iBPqXAQh2MM6 87H+IUZKDSUmUl3GiSKQQX1J+SmVGYnFGfFFpTmrxIUYZDg4lCd6ri4FygkWp6akVaZk5wECD SUtw8CiJ8G5eBJTmLS5IzC3OTIdInWJUlBLnbQfpEwBJZJTmwbXBgvsSo6yUMC8j0CFCPAWpR bmZJajyrxjFORiVhHl3gkzhycwrgZv+CmgxE9Di/j/CIItLEhFSUg2M1ctkDcSLn+/w9tH42n 7mrn5lxqKYJTVpC6IXPDkZPPN+VOAjUavDV/gKpn3oPOt7cN6pV5fV1dN5Tr36t99oo6rP9kW nBevjucP7TirbSxrtZ13IWaHOxlVuujRvs+rapVf7V7XPUT6xe+nyBuvHGUwekdcWbYvPPsB2 y3JqFRfnkyiXkip9JZbijERDLeai4kQAsbAGbWkCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-16.tower-27.messagelabs.com!1494525112!101336720!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 59437 invoked from network); 11 May 2017 17:51:53 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-16.tower-27.messagelabs.com with SMTP; 11 May 2017 17:51:53 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B10F1B93; Thu, 11 May 2017 10:51:52 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 756CF3F4FF; Thu, 11 May 2017 10:51:51 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 11 May 2017 18:53:32 +0100 Message-Id: <20170511175340.8448-21-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170511175340.8448-1-andre.przywara@arm.com> References: <20170511175340.8448-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v9 20/28] ARM: GICv3: handle unmapped LPIs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP When LPIs get unmapped by a guest, they might still be in some LR of some VCPU. Nevertheless we remove the corresponding pending_irq (possibly freeing it), and detect this case (irq_to_pending() returns NULL) when the LR gets cleaned up later. However a *new* LPI may get mapped with the same number while the old LPI is *still* in some LR. To avoid getting the wrong state, we mark every newly mapped LPI as PRISTINE, which means: has never been in an LR before. If we detect the LPI in an LR anyway, it must have been an older one, which we can simply retire. Before inserting such a PRISTINE LPI into an LR, we must make sure that it's not already in another LR, as the architecture forbids two interrupts with the same virtual IRQ number on one CPU. Signed-off-by: Andre Przywara --- xen/arch/arm/gic.c | 55 +++++++++++++++++++++++++++++++++++++++++----- xen/include/asm-arm/vgic.h | 6 +++++ 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index fd3fa05..8bf0578 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -375,6 +375,8 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, { ASSERT(!local_irq_is_enabled()); + clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); + gic_hw_ops->update_lr(lr, p, state); set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); @@ -442,12 +444,41 @@ void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) #endif } +/* + * Find an unused LR to insert an IRQ into. If this new interrupt is a + * PRISTINE LPI, scan the other LRs to avoid inserting the same IRQ twice. + */ +static int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, int lr) +{ + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status) ) + { + int used_lr = 0; + + while ( (used_lr = find_next_bit(lr_mask, nr_lrs, used_lr)) < nr_lrs ) + { + gic_hw_ops->read_lr(used_lr, &lr_val); + if ( lr_val.virq == p->irq ) + return used_lr; + } + } + + lr = find_next_zero_bit(lr_mask, nr_lrs, lr); + + return lr; +} + void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { - int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; struct pending_irq *p = irq_to_pending(v, virtual_irq); + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + int i = nr_lrs; ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -457,7 +488,8 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) { - i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); + i = gic_find_unused_lr(v, p, 0); + if (i < nr_lrs) { set_bit(i, &this_cpu(lr_mask)); gic_set_lr(i, p, GICH_LR_PENDING); @@ -509,7 +541,17 @@ static void gic_update_one_lr(struct vcpu *v, int i) } else if ( lr_val.state & GICH_LR_PENDING ) { - int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + int q __attribute__ ((unused)); + + if ( test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status) ) + { + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + return; + } + + q = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); #ifdef GIC_DEBUG if ( q ) gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", @@ -521,6 +563,9 @@ static void gic_update_one_lr(struct vcpu *v, int i) gic_hw_ops->clear_lr(i); clear_bit(i, &this_cpu(lr_mask)); + if ( test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status) ) + return; + if ( p->desc != NULL ) clear_bit(_IRQ_INPROGRESS, &p->desc->status); clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); @@ -591,7 +636,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) inflight_r = &v->arch.vgic.inflight_irqs; list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) { - lr = find_next_zero_bit(&this_cpu(lr_mask), nr_lrs, lr); + lr = gic_find_unused_lr(v, p, lr); if ( lr >= nr_lrs ) { /* No more free LRs: find a lower priority irq to evict */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 02732db..3fc4ceb 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -60,12 +60,18 @@ struct pending_irq * vcpu while it is still inflight and on an GICH_LR register on the * old vcpu. * + * GIC_IRQ_GUEST_PRISTINE_LPI: the IRQ is a newly mapped LPI, which + * has never been in an LR before. This means that any trace of an + * LPI with the same number in an LR must be from an older LPI, which + * has been unmapped before. + * */ #define GIC_IRQ_GUEST_QUEUED 0 #define GIC_IRQ_GUEST_ACTIVE 1 #define GIC_IRQ_GUEST_VISIBLE 2 #define GIC_IRQ_GUEST_ENABLED 3 #define GIC_IRQ_GUEST_MIGRATING 4 +#define GIC_IRQ_GUEST_PRISTINE_LPI 5 unsigned long status; struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */ unsigned int irq;