From patchwork Thu May 11 17:53:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9722649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E9E6460236 for ; Thu, 11 May 2017 17:53:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA0F7286D0 for ; Thu, 11 May 2017 17:53:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DEB64286E5; Thu, 11 May 2017 17:53:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8578B286D0 for ; Thu, 11 May 2017 17:53:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFu-000123-4x; Thu, 11 May 2017 17:52:02 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFs-0000ym-SH for xen-devel@lists.xenproject.org; Thu, 11 May 2017 17:52:00 +0000 Received: from [85.158.137.68] by server-8.bemta-3.messagelabs.com id B9/0B-02183-0C4A4195; Thu, 11 May 2017 17:52:00 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTXf/EpF Ig8tTFC2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oyO7XOZCpZJVrRvOs3SwLhRuIuRi0NIYDOj xOm73UxdjJxAznJGiSUHfEBsNgFdiR03XzOD2CICoRJPF3xnBmlgFljDKHFu0U82kISwgLnE8 YeLwIpYBFQlds4/CRbnFbCW2LDyBlhcQkBOouH8fTCbEyi+ZPosFohlVhK7dp9mncDIvYCRYR WjRnFqUVlqka6RsV5SUWZ6RkluYmaOrqGBsV5uanFxYnpqTmJSsV5yfu4mRqCH6xkYGHcw9u3 1O8QoycGkJMrLOFEkUogvKT+lMiOxOCO+qDQntfgQowwHh5IErz0wYIQEi1LTUyvSMnOAoQaT luDgURLhvb8YKM1bXJCYW5yZDpE6xagoJc4rCNInAJLIKM2Da4OF9yVGWSlhXkYGBgYhnoLUo tzMElT5V4ziHIxKwrzGIFN4MvNK4Ka/AlrMBLS4/48wyOKSRISUVAPj5Ht7LdbLBc+/dnpNpN lUzX+Or2ZK/2/zmvJctUQrI5pz09JF+etNHfSNI9asfPvSeevSLZ8u6Bxg2rMkeoHE7hSWT1r Hl85acHN3qJC7/KRTlgYTP6y6FD7Dc8KXJ28npr83KPsvp3BkycTH3vc37b5TFjP5lRKL5Lb7 IgvdDLQvaHKvXXtA9Y4SS3FGoqEWc1FxIgCTSfXeagIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-9.tower-31.messagelabs.com!1494525118!44544510!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 52246 invoked from network); 11 May 2017 17:51:59 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-31.messagelabs.com with SMTP; 11 May 2017 17:51:59 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A12021BB1; Thu, 11 May 2017 10:51:58 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A05A3F4FF; Thu, 11 May 2017 10:51:57 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 11 May 2017 18:53:36 +0100 Message-Id: <20170511175340.8448-25-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170511175340.8448-1-andre.przywara@arm.com> References: <20170511175340.8448-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v9 24/28] ARM: vITS: handle INV command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The INV command instructs the ITS to update the configuration data for a given LPI by re-reading its entry from the property table. We don't need to care so much about the priority value, but enabling or disabling an LPI has some effect: We remove or push virtual LPIs to their VCPUs, also check the virtual pending bit if an LPI gets enabled. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3-its.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index f7a8d77..6cfb560 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -456,6 +456,73 @@ static int update_lpi_property(struct domain *d, struct pending_irq *p) return 0; } +/* + * Checks whether an LPI that got enabled or disabled needs to change + * something in the VGIC (added or removed from the LR or queues). + * Must be called with the VCPU VGIC lock held. + */ +static void update_lpi_vgic_status(struct vcpu *v, struct pending_irq *p) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + if ( !list_empty(&p->inflight) && + !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v, p->irq, p->lpi_priority); + } + else + { + clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + list_del_init(&p->lr_queue); + } +} + +static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr) +{ + struct domain *d = its->d; + uint32_t devid = its_cmd_get_deviceid(cmdptr); + uint32_t eventid = its_cmd_get_id(cmdptr); + struct pending_irq *p; + unsigned long flags; + struct vcpu *vcpu; + uint32_t vlpi; + int ret = -1; + + spin_lock(&its->its_lock); + + /* Translate the event into a vCPU/vLPI pair. */ + if ( !read_itte_locked(its, devid, eventid, &vcpu, &vlpi) ) + goto out_unlock_its; + + if ( vlpi == INVALID_LPI ) + goto out_unlock_its; + + p = gicv3_its_get_event_pending_irq(d, its->doorbell_address, + devid, eventid); + if ( unlikely(!p) ) + goto out_unlock_its; + + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + + /* Read the property table and update our cached status. */ + if ( update_lpi_property(d, p) ) + goto out_unlock; + + /* Check whether the LPI needs to go on a VCPU. */ + update_lpi_vgic_status(vcpu, p); + + ret = 0; + +out_unlock: + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + +out_unlock_its: + spin_unlock(&its->its_lock); + + return ret; +} + /* Must be called with the ITS lock held. */ static int its_discard_event(struct virt_its *its, uint32_t vdevid, uint32_t vevid) @@ -782,6 +849,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) case GITS_CMD_INT: ret = its_handle_int(its, command); break; + case GITS_CMD_INV: + ret = its_handle_inv(its, command); + break; case GITS_CMD_MAPC: ret = its_handle_mapc(its, command); break;