From patchwork Thu May 11 17:53:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9722645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B45D160236 for ; Thu, 11 May 2017 17:53:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2681286D0 for ; Thu, 11 May 2017 17:53:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6E76286E5; Thu, 11 May 2017 17:53:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49D30286D0 for ; Thu, 11 May 2017 17:53:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFv-00014Z-CI; Thu, 11 May 2017 17:52:03 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d8sFu-00011h-HJ for xen-devel@lists.xenproject.org; Thu, 11 May 2017 17:52:02 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id 9D/F3-01977-1C4A4195; Thu, 11 May 2017 17:52:01 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTffgEpF Ig4tzGS2+b5nM5MDocfjDFZYAxijWzLyk/IoE1owNC94wFyyRrlgw/TBTA2O7SBcjF4eQwGZG iRXfD7FDOMsZJebfbwVyODnYBHQldtx8zQxiiwiESjxd8J0ZpIhZYA2jxLlFP9lAEsICVhILf j5mBLFZBFQlrszqYupi5ODgFbCWuPNLASQsISAn0XD+PtgcTqDwkumzWEBsIaDWXbtPs05g5F 7AyLCKUb04tagstUjXWC+pKDM9oyQ3MTNH19DAWC83tbg4MT01JzGpWC85P3cTI9C/DECwg7H 5i9MhRkkOJiVRXsaJIpFCfEn5KZUZicUZ8UWlOanFhxhlODiUJHivLgbKCRalpqdWpGXmAAMN Ji3BwaMkwnsfJM1bXJCYW5yZDpE6xagoJc4rCAxPIQGQREZpHlwbLLgvMcpKCfMyAh0ixFOQW pSbWYIq/4pRnINRSZh3J8h4nsy8Erjpr4AWMwEt7v8jDLK4JBEhJdXAOP2ZaidLad+mdVm5aY yVsly3ryz74zVDVlL2R3PJJIbDM/c8vPQhpO3tpHp/gbk+gf8C3/QreVwUfhpralo/e+ddz8f hX74rLg3RvaOQk8VuqVfUv6c1dHb1q9PRFyPL9s7O+/8nLnTuyUgLDnvhDOewm9sPz+O8/fWQ bYrukjtcZxmsN+ypVGIpzkg01GIuKk4EAGQuL2JpAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-9.tower-31.messagelabs.com!1494525120!44544513!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 52315 invoked from network); 11 May 2017 17:52:00 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-31.messagelabs.com with SMTP; 11 May 2017 17:52:00 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0DC171BBC; Thu, 11 May 2017 10:52:00 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB9EE3F4FF; Thu, 11 May 2017 10:51:58 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 11 May 2017 18:53:37 +0100 Message-Id: <20170511175340.8448-26-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170511175340.8448-1-andre.przywara@arm.com> References: <20170511175340.8448-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v9 25/28] ARM: vITS: handle INVALL command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The INVALL command instructs an ITS to invalidate the configuration data for all LPIs associated with a given redistributor (read: VCPU). This is nasty to emulate exactly with our architecture, so we just iterate over all mapped LPIs and filter for those from that particular VCPU. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3-its.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 6cfb560..36faa16 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -523,6 +523,69 @@ out_unlock_its: return ret; } +/* + * INVALL updates the per-LPI configuration status for every LPI mapped to + * a particular redistributor. + * We iterate over all mapped LPIs in our radix tree and update those. + */ +static int its_handle_invall(struct virt_its *its, uint64_t *cmdptr) +{ + uint32_t collid = its_cmd_get_collection(cmdptr); + struct vcpu *vcpu; + struct pending_irq *pirqs[16]; + uint64_t vlpi = 0; /* 64-bit to catch overflows */ + unsigned int nr_lpis, i; + unsigned long flags; + int ret = 0; + + /* + * As this implementation walks over all mapped LPIs, it might take + * too long for a real guest, so we might want to revisit this + * implementation for DomUs. + * However this command is very rare, also we don't expect many + * LPIs to be actually mapped, so it's fine for Dom0 to use. + */ + ASSERT(is_hardware_domain(its->d)); + + spin_lock(&its->its_lock); + vcpu = get_vcpu_from_collection(its, collid); + spin_unlock(&its->its_lock); + + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + read_lock(&its->d->arch.vgic.pend_lpi_tree_lock); + + do + { + nr_lpis = radix_tree_gang_lookup(&its->d->arch.vgic.pend_lpi_tree, + (void **)pirqs, vlpi, + ARRAY_SIZE(pirqs)); + + for ( i = 0; i < nr_lpis; i++ ) + { + /* We only care about LPIs on our VCPU. */ + if ( pirqs[i]->lpi_vcpu_id != vcpu->vcpu_id ) + continue; + + vlpi = pirqs[i]->irq; + /* If that fails for a single LPI, carry on to handle the rest. */ + ret = update_lpi_property(its->d, pirqs[i]); + if ( !ret ) + update_lpi_vgic_status(vcpu, pirqs[i]); + } + /* + * Loop over the next gang of pending_irqs until we reached the end of + * a (fully populated) tree or the lookup function returns less LPIs than + * it has been asked for. + */ + } while ( (++vlpi < its->d->arch.vgic.nr_lpis) && + (nr_lpis == ARRAY_SIZE(pirqs)) ); + + read_unlock(&its->d->arch.vgic.pend_lpi_tree_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + + return ret; +} + /* Must be called with the ITS lock held. */ static int its_discard_event(struct virt_its *its, uint32_t vdevid, uint32_t vevid) @@ -852,6 +915,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) case GITS_CMD_INV: ret = its_handle_inv(its, command); break; + case GITS_CMD_INVALL: + ret = its_handle_invall(its, command); + break; case GITS_CMD_MAPC: ret = its_handle_mapc(its, command); break;