diff mbox

[v10,12/32] ARM: GICv3: enable ITS and LPIs on the host

Message ID 20170526173540.10066-13-andre.przywara@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Andre Przywara May 26, 2017, 5:35 p.m. UTC 
Now that the host part of the ITS code is in place, we can enable the
ITS and also LPIs on each redistributor to get the show rolling.
At this point there would be no LPIs mapped, as guests don't know about
the ITS yet.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/gic-v3-its.c |  4 ++++
 xen/arch/arm/gic-v3.c     | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

Comments

Julien Grall May 30, 2017, 11:58 a.m. UTC | #1 
Hi Andre,

On 26/05/17 18:35, Andre Przywara wrote:
> Now that the host part of the ITS code is in place, we can enable the
> ITS and also LPIs on each redistributor to get the show rolling.
> At this point there would be no LPIs mapped, as guests don't know about
> the ITS yet.

In that case, why don't we move this patch at the beginning of the 
series? This would make easier to bisect this series as without it the 
ITS will not process commands and therefore initialization will fail.

>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
>  xen/arch/arm/gic-v3-its.c |  4 ++++
>  xen/arch/arm/gic-v3.c     | 18 ++++++++++++++++++
>  2 files changed, 22 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
> index 07280b3..aebc257 100644
> --- a/xen/arch/arm/gic-v3-its.c
> +++ b/xen/arch/arm/gic-v3-its.c
> @@ -505,6 +505,10 @@ static int gicv3_its_init_single_its(struct host_its *hw_its)
>          return -ENOMEM;
>      writeq_relaxed(0, hw_its->its_base + GITS_CWRITER);
>
> +    /* Now enable interrupt translation and command processing on that ITS. */
> +    reg = readl_relaxed(hw_its->its_base + GITS_CTLR);
> +    writel_relaxed(reg | GITS_CTLR_ENABLE, hw_its->its_base + GITS_CTLR);
> +
>      return 0;
>  }
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 8140c5f..d539d6c 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -620,6 +620,21 @@ static int gicv3_enable_redist(void)
>      return 0;
>  }
>
> +/* Enable LPIs on this redistributor (only useful when the host has an ITS). */
> +static bool gicv3_enable_lpis(void)
> +{
> +    uint32_t val;
> +
> +    val = readl_relaxed(GICD_RDIST_BASE + GICR_TYPER);
> +    if ( !(val & GICR_TYPER_PLPIS) )
> +        return false;
> +
> +    val = readl_relaxed(GICD_RDIST_BASE + GICR_CTLR);
> +    writel_relaxed(val | GICR_CTLR_ENABLE_LPIS, GICD_RDIST_BASE + GICR_CTLR);
> +
> +    return true;
> +}
> +
>  static int __init gicv3_populate_rdist(void)
>  {
>      int i;
> @@ -731,11 +746,14 @@ static int gicv3_cpu_init(void)
>      if ( gicv3_enable_redist() )
>          return -ENODEV;
>
> +    /* If the host has any ITSes, enable LPIs now. */
>      if ( gicv3_its_host_has_its() )
>      {
>          ret = gicv3_its_setup_collection(smp_processor_id());
>          if ( ret )
>              return ret;
> +        if ( !gicv3_enable_lpis() )
> +            return -EBUSY;
>      }
>
>      /* Set priority on PPI and SGI interrupts */
>
diff mbox

Patch

diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
index 07280b3..aebc257 100644
--- a/xen/arch/arm/gic-v3-its.c
+++ b/xen/arch/arm/gic-v3-its.c
@@ -505,6 +505,10 @@  static int gicv3_its_init_single_its(struct host_its *hw_its)
         return -ENOMEM;
     writeq_relaxed(0, hw_its->its_base + GITS_CWRITER);
 
+    /* Now enable interrupt translation and command processing on that ITS. */
+    reg = readl_relaxed(hw_its->its_base + GITS_CTLR);
+    writel_relaxed(reg | GITS_CTLR_ENABLE, hw_its->its_base + GITS_CTLR);
+
     return 0;
 }
 
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 8140c5f..d539d6c 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -620,6 +620,21 @@  static int gicv3_enable_redist(void)
     return 0;
 }
 
+/* Enable LPIs on this redistributor (only useful when the host has an ITS). */
+static bool gicv3_enable_lpis(void)
+{
+    uint32_t val;
+
+    val = readl_relaxed(GICD_RDIST_BASE + GICR_TYPER);
+    if ( !(val & GICR_TYPER_PLPIS) )
+        return false;
+
+    val = readl_relaxed(GICD_RDIST_BASE + GICR_CTLR);
+    writel_relaxed(val | GICR_CTLR_ENABLE_LPIS, GICD_RDIST_BASE + GICR_CTLR);
+
+    return true;
+}
+
 static int __init gicv3_populate_rdist(void)
 {
     int i;
@@ -731,11 +746,14 @@  static int gicv3_cpu_init(void)
     if ( gicv3_enable_redist() )
         return -ENODEV;
 
+    /* If the host has any ITSes, enable LPIs now. */
     if ( gicv3_its_host_has_its() )
     {
         ret = gicv3_its_setup_collection(smp_processor_id());
         if ( ret )
             return ret;
+        if ( !gicv3_enable_lpis() )
+            return -EBUSY;
     }
 
     /* Set priority on PPI and SGI interrupts */