From patchwork Fri May 26 17:35:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9750909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F8A360390 for ; Fri, 26 May 2017 17:38:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5C2E281B7 for ; Fri, 26 May 2017 17:38:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA7C3283B9; Fri, 26 May 2017 17:38:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 76FA5283C8 for ; Fri, 26 May 2017 17:38:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dEJ9U-0004z3-8I; Fri, 26 May 2017 17:35:52 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dEJ9T-0004yk-8U for xen-devel@lists.xenproject.org; Fri, 26 May 2017 17:35:51 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 42/2E-11537-67768295; Fri, 26 May 2017 17:35:50 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTbc0XSP SoG2llcX3LZOZHBg9Dn+4whLAGMWamZeUX5HAmnH2x1+2gokKFRdvdjE2MK6Q6GLk5BAS2MQo cXp6XBcjF5C9nFGib/4PRpAEm4CuxI6br5lBbBGBUImnC74zgxQxC6xhlGj/9JQVJCEsECix6 8BzNhCbRUBV4tTBM2BxXgFrideNt9lBbAkBOYmG8/fBBnEK2EjMOvuZCWKztcSbrd9ZJzByL2 BkWMWoUZxaVJZapGtkqpdUlJmeUZKbmJmja2hgrJebWlycmJ6ak5hUrJecn7uJEejhegYGxh2 MrSf8DjFKcjApifJOX6ceKcSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mCd1KaRqSQYFFqempFWmYO MNRg0hIcPEoivPNA0rzFBYm5xZnpEKlTjIpS4rxBIAkBkERGaR5cGyy8LzHKSgnzMjIwMAjxF KQW5WaWoMq/YhTnYFQS5mUCmcKTmVcCN/0V0GImoMW+59RBFpckIqSkGhj5Tqt/EWWZanh04Q WG/++jekIYhDuX5qZfKTDdu893n43V1tpN1pfDrG9u2//bdK976Pn3AdI1y3yNT+nl/pEX2hH nc3fBnYIPqrdeNQYU/NM5Hxs9PUdsgvg6nmqhDYo/dv3bduPExWPhS/yOrfJfEhz+PfV31Dul zrviQfx/jmxPWlitsO6bEktxRqKhFnNRcSIAORogjGoCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1495820149!99469811!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 14833 invoked from network); 26 May 2017 17:35:49 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 26 May 2017 17:35:49 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D602F80D; Fri, 26 May 2017 10:35:48 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B7B63F53D; Fri, 26 May 2017 10:35:47 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 26 May 2017 18:35:10 +0100 Message-Id: <20170526173540.10066-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170526173540.10066-1-andre.przywara@arm.com> References: <20170526173540.10066-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v10 02/32] ARM: GICv3: setup number of LPI bits for a GICv3 guest X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The host supports a certain number of LPI identifiers, as stored in the GICD_TYPER register. Store this number from the hardware register in vgic_v3_hw to allow injecting the very same number into a guest (Dom0). DomUs get the legacy number of 10 bits here, since for now it only sees SPIs, so it does not need more. This should be revisited once we get proper DomU ITS support. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 6 +++++- xen/arch/arm/vgic-v3.c | 10 +++++++++- xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/vgic.h | 3 ++- 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a559e5e..29c8964 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1579,6 +1579,7 @@ static int __init gicv3_init(void) { int res, i; uint32_t reg; + unsigned int intid_bits; if ( !cpu_has_gicv3 ) { @@ -1622,8 +1623,11 @@ static int __init gicv3_init(void) i, r->base, r->base + r->size); } + reg = readl_relaxed(GICD + GICD_TYPER); + intid_bits = GICD_TYPE_ID_BITS(reg); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, - gicv3.rdist_stride); + gicv3.rdist_stride, intid_bits); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index d10757a..87f5fb3 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -57,18 +57,21 @@ static struct { unsigned int nr_rdist_regions; const struct rdist_region *regions; uint32_t rdist_stride; /* Re-distributor stride */ + unsigned int intid_bits; /* Number of interrupt ID bits */ } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride) + uint32_t rdist_stride, + unsigned int intid_bits) { vgic_v3_hw.enabled = 1; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; vgic_v3_hw.rdist_stride = rdist_stride; + vgic_v3_hw.intid_bits = intid_bits; } static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter) @@ -1482,6 +1485,8 @@ static int vgic_v3_domain_init(struct domain *d) first_cpu += size / d->arch.vgic.rdist_stride; } + + d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; } else { @@ -1497,6 +1502,9 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE; d->arch.vgic.rdist_regions[0].first_cpu = 0; + + /* TODO: only SPIs for now, adjust this when guests need LPIs */ + d->arch.vgic.intid_bits = 10; } ret = vgic_v3_its_init_domain(d); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 6de8082..7c3829d 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -111,6 +111,7 @@ struct arch_domain uint32_t rdist_stride; /* Re-Distributor stride */ struct rb_root its_devices; /* Devices mapped to an ITS */ spinlock_t its_devices_lock; /* Protects the its_devices tree */ + unsigned int intid_bits; #endif } vgic; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 544867a..df75064 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -346,7 +346,8 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride); + uint32_t rdist_stride, + unsigned int intid_bits); #endif #endif /* __ASM_ARM_VGIC_H__ */