From patchwork Fri Jun 9 17:41:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9778999 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E5CE160318 for ; Fri, 9 Jun 2017 17:44:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D26F7286F8 for ; Fri, 9 Jun 2017 17:44:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C632228702; Fri, 9 Jun 2017 17:44:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2AC7F286F8 for ; Fri, 9 Jun 2017 17:44:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNvK-0003zH-H5; Fri, 09 Jun 2017 17:42:14 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNvI-0003uA-II for xen-devel@lists.xenproject.org; Fri, 09 Jun 2017 17:42:12 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id 35/59-01985-3FDDA395; Fri, 09 Jun 2017 17:42:11 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTffzXat Ig1t3+Sy+b5nM5MDocfjDFZYAxijWzLyk/IoE1oytk7+yF6zSqdjZ84OpgfGCYhcjF4eQwGZG ia7fq5ghnOWMEpeOzGTtYuTkYBPQldhx8zUziC0iECrxdMF3sCJmgeuMEqd3zGcDSQgLuEs0v nrOCGKzCKhKfDm5hAXE5hWwlth6+ClYjYSAnETD+ftggziB4tv2rAWLCwlYSbQcusw+gZF7AS PDKkb14tSistQiXUu9pKLM9IyS3MTMHF1DA2O93NTi4sT01JzEpGK95PzcTYxAD9czMDDuYHz 90+kQoyQHk5Io77QCq0ghvqT8lMqMxOKM+KLSnNTiQ4wyHBxKErx/bwPlBItS01Mr0jJzgKEG k5bg4FES4X1xEijNW1yQmFucmQ6ROsWoKCXOa3kHKCEAksgozYNrg4X3JUZZKWFeRgYGBiGeg tSi3MwSVPlXjOIcjErCvLtApvBk5pXATX8FtJgJaPGSdxYgi0sSEVJSDYwhB5jFtkme/az6oW yT6Mu77tMf/gk72LLL0HdLRn7NnvM1L9g1/3n5Hn5aVGNn+bWR+UdXy7fvZy2+XS6yXOFtL57 xdL6j2lpZ/mUP3QMOzvqsUnbjYf20/3s+Pvrqc3DdwwlWO56J2y67alm89eZfG2eb+gWaqf+q WKSeLH1+v7CE/73mG7duJZbijERDLeai4kQA7/aIsGoCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1497030130!104928204!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30465 invoked from network); 9 Jun 2017 17:42:10 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-31.messagelabs.com with SMTP; 9 Jun 2017 17:42:10 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 545DE15BF; Fri, 9 Jun 2017 10:42:10 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0BB673F578; Fri, 9 Jun 2017 10:42:08 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 9 Jun 2017 18:41:27 +0100 Message-Id: <20170609174141.5068-21-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170609174141.5068-1-andre.przywara@arm.com> References: <20170609174141.5068-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni , Manish Jaggi Subject: [Xen-devel] [PATCH v11 20/34] ARM: vITS: introduce translation table walks X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The ITS stores the target (v)CPU and the (virtual) LPI number in tables. Introduce functions to walk those tables and translate an device ID - event ID pair into a pair of virtual LPI and vCPU. We map those tables on demand - which is cheap on arm64 - and copy the respective entries before using them, to avoid the guest tampering with them meanwhile. To allow compiling without warnings, we declare two functions as non-static for the moment, which two later patches will fix. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/vgic-v3-its.c | 140 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 5481791..36910aa 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -83,6 +83,7 @@ struct vits_itte * Each entry just contains the VCPU ID of the respective vCPU. */ typedef uint16_t coll_table_entry_t; +#define UNMAPPED_COLLECTION ((coll_table_entry_t)~0) /* * Our device table encodings: @@ -99,6 +100,145 @@ typedef uint64_t dev_table_entry_t; #define GITS_BASER_RO_MASK (GITS_BASER_TYPE_MASK | \ (0x1fL << GITS_BASER_ENTRY_SIZE_SHIFT)) +/* + * The physical address is encoded slightly differently depending on + * the used page size: the highest four bits are stored in the lowest + * four bits of the field for 64K pages. + */ +static paddr_t get_baser_phys_addr(uint64_t reg) +{ + if ( reg & BIT(9) ) + return (reg & GENMASK(47, 16)) | + ((reg & GENMASK(15, 12)) << 36); + else + return reg & GENMASK(47, 12); +} + +/* Must be called with the ITS lock held. */ +static struct vcpu *get_vcpu_from_collection(struct virt_its *its, + uint16_t collid) +{ + paddr_t addr = get_baser_phys_addr(its->baser_coll); + coll_table_entry_t vcpu_id; + int ret; + + ASSERT(spin_is_locked(&its->its_lock)); + + if ( collid >= its->max_collections ) + return NULL; + + ret = vgic_access_guest_memory(its->d, + addr + collid * sizeof(coll_table_entry_t), + &vcpu_id, sizeof(coll_table_entry_t), false); + if ( ret ) + return NULL; + + if ( vcpu_id == UNMAPPED_COLLECTION || vcpu_id >= its->d->max_vcpus ) + return NULL; + + return its->d->vcpu[vcpu_id]; +} + +/* + * Lookup the address of the Interrupt Translation Table associated with + * that device ID. + * TODO: add support for walking indirect tables. + */ +static int its_get_itt(struct virt_its *its, uint32_t devid, + dev_table_entry_t *itt) +{ + paddr_t addr = get_baser_phys_addr(its->baser_dev); + + if ( devid >= its->max_devices ) + return -EINVAL; + + return vgic_access_guest_memory(its->d, + addr + devid * sizeof(dev_table_entry_t), + itt, sizeof(*itt), false); +} + +/* + * Lookup the address of the Interrupt Translation Table associated with + * a device ID and return the address of the ITTE belonging to the event ID + * (which is an index into that table). + */ +static paddr_t its_get_itte_address(struct virt_its *its, + uint32_t devid, uint32_t evid) +{ + dev_table_entry_t itt; + int ret; + + ret = its_get_itt(its, devid, &itt); + if ( ret ) + return INVALID_PADDR; + + if ( evid >= DEV_TABLE_ITT_SIZE(itt) || + DEV_TABLE_ITT_ADDR(itt) == INVALID_PADDR ) + return INVALID_PADDR; + + return DEV_TABLE_ITT_ADDR(itt) + evid * sizeof(struct vits_itte); +} + +/* + * Queries the collection and device tables to get the vCPU and virtual + * LPI number for a given guest event. This first accesses the guest memory + * to resolve the address of the ITTE, then reads the ITTE entry at this + * address and puts the result in vcpu_ptr and vlpi_ptr. + * Must be called with the ITS lock held. + */ +bool read_itte(struct virt_its *its, uint32_t devid, uint32_t evid, + struct vcpu **vcpu_ptr, uint32_t *vlpi_ptr) +{ + paddr_t addr; + struct vits_itte itte; + struct vcpu *vcpu; + + ASSERT(spin_is_locked(&its->its_lock)); + + addr = its_get_itte_address(its, devid, evid); + if ( addr == INVALID_PADDR ) + return false; + + if ( vgic_access_guest_memory(its->d, addr, &itte, sizeof(itte), false) ) + return false; + + vcpu = get_vcpu_from_collection(its, itte.collection); + if ( !vcpu ) + return false; + + *vcpu_ptr = vcpu; + *vlpi_ptr = itte.vlpi; + return true; +} + +/* + * Queries the collection and device tables to translate the device ID and + * event ID and find the appropriate ITTE. The given collection ID and the + * virtual LPI number are then stored into that entry. + * If vcpu_ptr is provided, returns the VCPU belonging to that collection. + * Must be called with the ITS lock held. + */ +bool write_itte(struct virt_its *its, uint32_t devid, + uint32_t evid, uint32_t collid, uint32_t vlpi) +{ + paddr_t addr; + struct vits_itte itte; + + ASSERT(spin_is_locked(&its->its_lock)); + + addr = its_get_itte_address(its, devid, evid); + if ( addr == INVALID_PADDR ) + return false; + + itte.collection = collid; + itte.vlpi = vlpi; + + if ( vgic_access_guest_memory(its->d, addr, &itte, sizeof(itte), true) ) + return false; + + return true; +} + /************************************** * Functions that handle ITS commands * **************************************/