From patchwork Fri Jun 9 17:41:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9778991 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 91DFA603B4 for ; Fri, 9 Jun 2017 17:43:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F2D5286E0 for ; Fri, 9 Jun 2017 17:43:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 744A0286E2; Fri, 9 Jun 2017 17:43:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BE3CD286E0 for ; Fri, 9 Jun 2017 17:43:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNvS-0004Gs-RW; Fri, 09 Jun 2017 17:42:22 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNvQ-000445-Va for xen-devel@lists.xenproject.org; Fri, 09 Jun 2017 17:42:21 +0000 Received: from [85.158.139.211] by server-2.bemta-5.messagelabs.com id CB/6E-02006-CFDDA395; Fri, 09 Jun 2017 17:42:20 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTffnXat Ig0+9whbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8aKi2oFPyQqjj6WaGDsFu5i5OIQEtjMKPGv aRtTFyMnkLOcUWLSXnYQm01AV2LHzdfMILaIQKjE0wXfmUEamAWuM0qc3jGfDSQhLGAlceT6X 7AiFgFViQl/m8HivALWElNWrwOLSwjISTScvw9mcwLFt+1ZywaxzEqi5dBl9gmM3AsYGVYxah SnFpWlFukaWeglFWWmZ5TkJmbm6BoamOrlphYXJ6an5iQmFesl5+duYgR6t56BgXEHY98qv0O MkhxMSqK80wqsIoX4kvJTKjMSizPii0pzUosPMcpwcChJ8L66A5QTLEpNT61Iy8wBhhlMWoKD R0mE98VJoDRvcUFibnFmOkTqFKOilDjvRpA+AZBERmkeXBsstC8xykoJ8zIyMDAI8RSkFuVml qDKv2IU52BUEuY1BEaKEE9mXgnc9FdAi5mAFi95ZwGyuCQRISXVwNjF+5+v6PFdBuFQPq1t6+ J6k1OFmU9M2jBjBt/tbkdxTq9Fc8+b64jerjhb0u92SkW1NrBoY7P4geB3LUscrG8kzZRW7Uw wqJErsdiS8mly75WTDyMqWn521XWq/26zObuR8bn9n1kF1j6tVRXFH4MdlKVunXkasiHl9JRL QqGbnrKcs7/Lp8RSnJFoqMVcVJwIAFqFMtZoAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-13.tower-206.messagelabs.com!1497030136!87189173!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 13152 invoked from network); 9 Jun 2017 17:42:17 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-206.messagelabs.com with SMTP; 9 Jun 2017 17:42:17 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A99E15BF; Fri, 9 Jun 2017 10:42:16 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32E233F578; Fri, 9 Jun 2017 10:42:15 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 9 Jun 2017 18:41:31 +0100 Message-Id: <20170609174141.5068-25-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170609174141.5068-1-andre.przywara@arm.com> References: <20170609174141.5068-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni , Manish Jaggi Subject: [Xen-devel] [PATCH v11 24/34] ARM: vITS: handle CLEAR command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This introduces the ITS command handler for the CLEAR command, which clears the pending state of an LPI. This removes a not-yet injected, but already queued IRQ from a VCPU. As read_itte() is now eventually used, we add the static keyword. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/vgic-v3-its.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 14cb1f0..f6262fc 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -52,6 +52,7 @@ */ struct virt_its { struct domain *d; + paddr_t doorbell_address; unsigned int devid_bits; unsigned int evid_bits; spinlock_t vcmd_lock; /* Protects the virtual command buffer, which */ @@ -323,6 +324,57 @@ static int its_handle_mapc(struct virt_its *its, uint64_t *cmdptr) return 0; } +/* + * CLEAR removes the pending state from an LPI. */ +static int its_handle_clear(struct virt_its *its, uint64_t *cmdptr) +{ + uint32_t devid = its_cmd_get_deviceid(cmdptr); + uint32_t eventid = its_cmd_get_id(cmdptr); + struct pending_irq *p; + struct vcpu *vcpu; + uint32_t vlpi; + unsigned long flags; + int ret = -1; + + spin_lock(&its->its_lock); + + /* Translate the DevID/EvID pair into a vCPU/vLPI pair. */ + if ( !read_itte(its, devid, eventid, &vcpu, &vlpi) ) + goto out_unlock; + + p = gicv3_its_get_event_pending_irq(its->d, its->doorbell_address, + devid, eventid); + /* Protect against an invalid LPI number. */ + if ( unlikely(!p) ) + goto out_unlock; + + /* + * TODO: This relies on the VCPU being correct in the ITS tables. + * This can be fixed by either using a per-IRQ lock or by using + * the VCPU ID from the pending_irq instead. + */ + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + + /* + * If the LPI is already visible on the guest, it is too late to + * clear the pending state. However this is a benign race that can + * happen on real hardware, too: If the LPI has already been forwarded + * to a CPU interface, a CLEAR request reaching the redistributor has + * no effect on that LPI anymore. Since LPIs are edge triggered and + * have no active state, we don't need to care about this here. + */ + if ( !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_remove_irq(vcpu, p); + + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + ret = 0; + +out_unlock: + spin_unlock(&its->its_lock); + + return ret; +} + #define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12) #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5)) @@ -359,6 +411,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) switch ( its_cmd_get_command(command) ) { + case GITS_CMD_CLEAR: + ret = its_handle_clear(its, command); + break; case GITS_CMD_INT: ret = its_handle_int(its, command); break;