From patchwork Fri Jun 9 17:41:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9779011 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5A1EE60318 for ; Fri, 9 Jun 2017 17:44:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47161286E0 for ; Fri, 9 Jun 2017 17:44:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BE50286E7; Fri, 9 Jun 2017 17:44:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7672286E0 for ; Fri, 9 Jun 2017 17:44:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNut-0003Lg-7g; Fri, 09 Jun 2017 17:41:47 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dJNus-0003L6-6h for xen-devel@lists.xenproject.org; Fri, 09 Jun 2017 17:41:46 +0000 Received: from [85.158.139.211] by server-9.bemta-5.messagelabs.com id 81/0B-01999-9DDDA395; Fri, 09 Jun 2017 17:41:45 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTffGXat Ig7d3zSy+b5nM5MDocfjDFZYAxijWzLyk/IoE1owLa3uZCw4qVcxs3sPUwPhFsouRi0NIYDOj xOajy9khnOWMEhMnrWXsYuTkYBPQldhx8zUziC0iECrxdMF3ZpAiZoHrjBKnd8xnA0kICwRK/ L65HayIRUBVon3HQnYQm1fASmLvu1NgcQkBOYmG8/fBbE4Ba4lte9aC9QoB1bQcusw+gZF7AS PDKkb14tSistQiXUO9pKLM9IyS3MTMHF1DA1O93NTi4sT01JzEpGK95PzcTYxAD9czMDDuYGz qdT7EKMnBpCTKO63AKlKILyk/pTIjsTgjvqg0J7X4EKMMB4eSBO+rO0A5waLU9NSKtMwcYKjB pCU4eJREeF+cBErzFhck5hZnpkOkTjEqSonzbgTpEwBJZJTmwbXBwvsSo6yUMC8jAwODEE9Ba lFuZgmq/CtGcQ5GJWFeQ2C0CPFk5pXATX8FtJgJaPGSdxYgi0sSEVJSDYwFidY1vNGa148l5Y l2en2a/uNm9ReNQjkzDzmeZgtdm7+Mxm6LI07ZuZ02OfP8zl//da6rNubcNTe8+qNKx2/ew9A rsxwCnRc0cpkWmZvzLH/D4Wnc0zlz3sdy3sAO1/d/3q0W5mbrXdjrtlkn+q7pTovo2xX2ZTFr 5Zg8xQvefpA7L5mtpMRSnJFoqMVcVJwIAFfBzlpqAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-4.tower-206.messagelabs.com!1497030104!102671284!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48118 invoked from network); 9 Jun 2017 17:41:44 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-4.tower-206.messagelabs.com with SMTP; 9 Jun 2017 17:41:44 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE4A01596; Fri, 9 Jun 2017 10:41:43 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75E2E3F578; Fri, 9 Jun 2017 10:41:42 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 9 Jun 2017 18:41:11 +0100 Message-Id: <20170609174141.5068-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170609174141.5068-1-andre.przywara@arm.com> References: <20170609174141.5068-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni , Manish Jaggi Subject: [Xen-devel] [PATCH v11 04/34] ARM: GICv3: setup number of LPI bits for a GICv3 guest X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The host supports a certain number of LPI identifiers, as stored in the GICD_TYPER register. Store this number from the hardware register in vgic_v3_hw to allow injecting the very same number into a guest (Dom0). DomUs get the legacy number of 10 bits here, since for now it only sees SPIs, so it does not need more. This should be revisited once we get proper DomU ITS support. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/gic-v3.c | 6 +++++- xen/arch/arm/vgic-v3.c | 16 +++++++++++++++- xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/vgic.h | 3 ++- 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index eda3410..fc3614e 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1597,6 +1597,7 @@ static int __init gicv3_init(void) { int res, i; uint32_t reg; + unsigned int intid_bits; if ( !cpu_has_gicv3 ) { @@ -1640,8 +1641,11 @@ static int __init gicv3_init(void) i, r->base, r->base + r->size); } + reg = readl_relaxed(GICD + GICD_TYPER); + intid_bits = GICD_TYPE_ID_BITS(reg); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, - gicv3.rdist_stride); + gicv3.rdist_stride, intid_bits); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 8abc069..2b2b4e9 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -57,18 +57,21 @@ static struct { unsigned int nr_rdist_regions; const struct rdist_region *regions; uint32_t rdist_stride; /* Re-distributor stride */ + unsigned int intid_bits; /* Number of interrupt ID bits */ } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride) + uint32_t rdist_stride, + unsigned int intid_bits) { vgic_v3_hw.enabled = 1; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; vgic_v3_hw.rdist_stride = rdist_stride; + vgic_v3_hw.intid_bits = intid_bits; } static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter) @@ -1485,6 +1488,8 @@ static int vgic_v3_domain_init(struct domain *d) first_cpu += size / d->arch.vgic.rdist_stride; } + + d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; } else { @@ -1500,6 +1505,15 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE; d->arch.vgic.rdist_regions[0].first_cpu = 0; + + /* + * TODO: only SPIs for now, adjust this when guests need LPIs. + * Please note that this value just describes the bits required + * in the stream interface, which is of no real concern for our + * emulation. So we just go with "10" here to cover all eventual + * SPIs (even if the guest implements less). + */ + d->arch.vgic.intid_bits = 10; } ret = vgic_v3_its_init_domain(d); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 6de8082..7c3829d 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -111,6 +111,7 @@ struct arch_domain uint32_t rdist_stride; /* Re-Distributor stride */ struct rb_root its_devices; /* Devices mapped to an ITS */ spinlock_t its_devices_lock; /* Protects the its_devices tree */ + unsigned int intid_bits; #endif } vgic; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 544867a..df75064 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -346,7 +346,8 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride); + uint32_t rdist_stride, + unsigned int intid_bits); #endif #endif /* __ASM_ARM_VGIC_H__ */