From patchwork Wed Jun 14 16:52:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9786973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 906FB60325 for ; Wed, 14 Jun 2017 16:54:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82219285E6 for ; Wed, 14 Jun 2017 16:54:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 754921FF15; Wed, 14 Jun 2017 16:54:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0505E1FF15 for ; Wed, 14 Jun 2017 16:54:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLBX0-0006TR-Ay; Wed, 14 Jun 2017 16:52:34 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLBWz-0006RJ-DM for xen-devel@lists.xenproject.org; Wed, 14 Jun 2017 16:52:33 +0000 Received: from [85.158.137.68] by server-17.bemta-3.messagelabs.com id ED/AF-02955-0D961495; Wed, 14 Jun 2017 16:52:32 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTfdCpmO kwe9rbBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8be3SdYC64pV5yZ8o6pgbFDtouRi0NIYDOj xOe5B9khnOWMEst/NTF3MXJysAnoSuy4+RrMFhEIlXi64DszSBGzwHVGidM75rOBJIQFwiTeX e5mBbFZBFQlTjXeBopzcPAKWEs0Ho8CCUsIyEk0nL8PNocTKDx1+2QmkBIhASuJmyv0JzByL2 BkWMWoUZxaVJZapGtorJdUlJmeUZKbmJmja2hgrJebWlycmJ6ak5hUrJecn7uJEehfBiDYwbh tu+chRkkOJiVR3qmCjpFCfEn5KZUZicUZ8UWlOanFhxhlODiUJHgPZwDlBItS01Mr0jJzgIEG k5bg4FES4d2aCpTmLS5IzC3OTIdInWJUlBLnPQvSJwCSyCjNg2uDBfclRlkpYV5GoEOEeApSi 3IzS1DlXzGKczAqCfOWpQNN4cnMK4Gb/gpoMRPQ4qALDiCLSxIRUlINjJK1nfUiT7dn3Ht/rJ kjr1+/dHaxSZKAmdDjafozrrAZXgmeVeiy9nvXjk3qW11FEtk2Pkyd9WpSfWRM42bu+zYLPi3 Rnr7up+3Fd14XF/7+2eCgl/uyKK7ltvaytqqUo/+zrmlfmH/U9VJkasK51cLh04oc7x1vOr1+ jbHqJpNfH2/m32SbtE6JpTgj0VCLuag4EQDfFuohaQIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1497459151!104963744!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 29072 invoked from network); 14 Jun 2017 16:52:31 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-31.messagelabs.com with SMTP; 14 Jun 2017 16:52:31 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32A2B15B2; Wed, 14 Jun 2017 09:52:31 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D79773F3E1; Wed, 14 Jun 2017 09:52:29 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 14 Jun 2017 17:52:00 +0100 Message-Id: <20170614165223.7543-12-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170614165223.7543-1-andre.przywara@arm.com> References: <20170614165223.7543-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni , Manish Jaggi Subject: [Xen-devel] [PATCH v12 11/34] ARM: vGIC: cache virtual LPI priority in struct pending_irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP We enhance struct pending_irq to cache the priority information for LPIs. Reading the information from there is faster than accessing the property table from guest memory. Also it use some padding area in the struct, so does not require more memory. This introduces the function to retrieve the LPI priority as a vgic_ops. Also this moves the vgic_get_virq_priority() call in vgic_vcpu_inject_irq() to happen after the NULL check of the pending_irq pointer, so we can rely on the pointer in the new function. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/vgic-v2.c | 7 +++++++ xen/arch/arm/vgic-v3.c | 11 +++++++++++ xen/arch/arm/vgic.c | 10 +++++++--- xen/include/asm-arm/vgic.h | 2 ++ 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 488e6fa..4f8dee4 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -712,11 +712,18 @@ static struct pending_irq *vgic_v2_lpi_to_pending(struct domain *d, BUG(); } +static int vgic_v2_lpi_get_priority(struct domain *d, unsigned int vlpi) +{ + /* Dummy function, no LPIs on a VGICv2. */ + BUG(); +} + static const struct vgic_ops vgic_v2_ops = { .vcpu_init = vgic_v2_vcpu_init, .domain_init = vgic_v2_domain_init, .domain_free = vgic_v2_domain_free, .lpi_to_pending = vgic_v2_lpi_to_pending, + .lpi_get_priority = vgic_v2_lpi_get_priority, .max_vcpus = 8, }; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 9dee2df..0b4669f 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1577,12 +1577,23 @@ static struct pending_irq *vgic_v3_lpi_to_pending(struct domain *d, return pirq; } +/* Retrieve the priority of an LPI from its struct pending_irq. */ +static int vgic_v3_lpi_get_priority(struct domain *d, uint32_t vlpi) +{ + struct pending_irq *p = vgic_v3_lpi_to_pending(d, vlpi); + + ASSERT(p); + + return p->lpi_priority; +} + static const struct vgic_ops v3_ops = { .vcpu_init = vgic_v3_vcpu_init, .domain_init = vgic_v3_domain_init, .domain_free = vgic_v3_domain_free, .emulate_reg = vgic_v3_emulate_reg, .lpi_to_pending = vgic_v3_lpi_to_pending, + .lpi_get_priority = vgic_v3_lpi_get_priority, /* * We use both AFF1 and AFF0 in (v)MPIDR. Thus, the max number of CPU * that can be supported is up to 4096(==256*16) in theory. diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index d7c4f32..204e0d9 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -227,8 +227,13 @@ struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq) static int vgic_get_virq_priority(struct vcpu *v, unsigned int virq) { - struct vgic_irq_rank *rank = vgic_rank_irq(v, virq); + struct vgic_irq_rank *rank; + + /* LPIs don't have a rank, also store their priority separately. */ + if ( is_lpi(virq) ) + return v->domain->arch.vgic.handler->lpi_get_priority(v->domain, virq); + rank = vgic_rank_irq(v, virq); return ACCESS_ONCE(rank->priority[virq & INTERRUPT_RANK_MASK]); } @@ -503,8 +508,6 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) unsigned long flags; bool running; - priority = vgic_get_virq_priority(v, virq); - spin_lock_irqsave(&v->arch.vgic.lock, flags); n = irq_to_pending(v, virq); @@ -530,6 +533,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) goto out; } + priority = vgic_get_virq_priority(v, virq); n->priority = priority; /* the irq is enabled */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 9dc487b..d1fcea1 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -72,6 +72,7 @@ struct pending_irq #define GIC_INVALID_LR (uint8_t)~0 uint8_t lr; uint8_t priority; + uint8_t lpi_priority; /* Caches the priority if this is an LPI. */ /* inflight is used to append instances of pending_irq to * vgic.inflight_irqs */ struct list_head inflight; @@ -136,6 +137,7 @@ struct vgic_ops { bool (*emulate_reg)(struct cpu_user_regs *regs, union hsr hsr); /* lookup the struct pending_irq for a given LPI interrupt */ struct pending_irq *(*lpi_to_pending)(struct domain *d, unsigned int vlpi); + int (*lpi_get_priority)(struct domain *d, uint32_t vlpi); /* Maximum number of vCPU supported */ const unsigned int max_vcpus; };