From patchwork Tue Jun 20 09:15:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 9798931 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 95F5B601BC for ; Tue, 20 Jun 2017 09:17:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8CB672810E for ; Tue, 20 Jun 2017 09:17:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 819482847A; Tue, 20 Jun 2017 09:17:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 14CEB2810E for ; Tue, 20 Jun 2017 09:17:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNFGI-00006T-6a; Tue, 20 Jun 2017 09:15:50 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNFGG-00005O-W6 for xen-devel@lists.xenproject.org; Tue, 20 Jun 2017 09:15:49 +0000 Received: from [193.109.254.147] by server-10.bemta-6.messagelabs.com id 45/02-03613-4C7E8495; Tue, 20 Jun 2017 09:15:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRWlGSWpSXmKPExsXitHRDpO7h5x6 RBt+X6Vh83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBnNd66xFTyXrGhac5KpgXGBcBcjJ4eEgL9E +52jrCA2m4COxMW5O9m6GDk4RARUJG7vNehi5OJgFtjAKHHux152kBphAQeJH5ufM4PYLAKqE tc+drCB2LwClhITnvxihJipJ/F24gswm1PASmLp0xZ2kJlCQDU9/8IgygUlTs58wgJiMwtoSr Ru/80OYctLNG+dDTZeSEBRon/eA7YJjHyzkLTMQtIyC0nLAkbmVYwaxalFZalFukaWeklFmek ZJbmJmTm6hgZmermpxcWJ6ak5iUnFesn5uZsYgaHGAAQ7GA8sCjzEKMnBpCTKu+COR6QQX1J+ SmVGYnFGfFFpTmrxIUYNDg6BzWtXX2CUYsnLz0tVkuCtfAZUJ1iUmp5akZaZA4wGmFIJDh4lE d7FIGN4iwsSc4sz0yFSpxgVpcR5eUH6BEASGaV5cG2wCLzEKCslzMsIdJQQT0FqUW5mCar8K0 ZxDkYlYd5GkCk8mXklcNNfAS1mAlr84gjY4pJEhJRUA2PWzD6t99HCCbtCdJSYDPu23tkWbpH zjPH9X4k2nsJwLy6Rzcq8tQ8d3iw3zjzx8Ppkllznhw/8sue9Oa9xQ+KHy7J3YhLzg+99630r Mutq8ioHWXZHQWOfnA6vjT+fiSwzmxHtaNct0X1XxE+4TYPvts5iVeNDZZ6+HelXmTSuh7Jcj 53apMRSnJFoqMVcVJwIAAzn2ra7AgAA X-Env-Sender: prvs=337a62209=roger.pau@citrix.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1497950145!99003087!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12778 invoked from network); 20 Jun 2017 09:15:47 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-13.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 20 Jun 2017 09:15:47 -0000 X-IronPort-AV: E=Sophos;i="5.39,364,1493683200"; d="scan'208";a="428603390" From: Roger Pau Monne To: Date: Tue, 20 Jun 2017 10:15:39 +0100 Message-ID: <20170620091539.59051-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.11.0 (Apple Git-81) In-Reply-To: <20170620091539.59051-1-roger.pau@citrix.com> References: <20170620091539.59051-1-roger.pau@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , boris.ostrovsky@oracle.com, Roger Pau Monne , Jan Beulich Subject: [Xen-devel] [PATCH v5 3/3] x86/vioapic: bind interrupts to PVH Dom0 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the glue in order to bind the PVH Dom0 GSI from bare metal. This is done when Dom0 unmasks the vIO APIC pins, by fetching the current pin settings and setting up the PIRQ, which will then be bound to Dom0. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper --- Changes since v4: - s/d/currd/. Changes since v3: - Setup the binding after writing the modified RTE fields back into the vIO APIC struct, or else pt_irq_create_bind will fetch the wrong trigger mode. Changes since v2: - s/vioapic_dom0_map_gsi/vioapic_hwdom_map_gsi/. - Don't set hvm_domid in xen_domctl_bind_pt_irq_t (it's ignored). - s/gdprintk/gprintk/. - Change the logic of the error paths and remove the labels. Changes since v1: - Mask the pin on error (instead of panicking). - Factor out the Dom0 specific code into a function. - Use the newly introduced allocate_and_map_gsi_pirq instead of physdev_map_pirq. --- xen/arch/x86/hvm/vioapic.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c index abcc473c88..f9f35e2713 100644 --- a/xen/arch/x86/hvm/vioapic.c +++ b/xen/arch/x86/hvm/vioapic.c @@ -158,6 +158,52 @@ static int vioapic_read( return X86EMUL_OKAY; } +static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig, + unsigned int pol) +{ + struct domain *currd = current->domain; + xen_domctl_bind_pt_irq_t pt_irq_bind = { + .irq_type = PT_IRQ_TYPE_PCI, + .machine_irq = gsi, + }; + int ret, pirq = gsi; + + ASSERT(is_hardware_domain(currd)); + + /* Interrupt has been unmasked, bind it now. */ + ret = mp_register_gsi(gsi, trig, pol); + if ( ret == -EEXIST ) + return 0; + if ( ret ) + { + gprintk(XENLOG_WARNING, "vioapic: error registering GSI %u: %d\n", + gsi, ret); + return ret; + } + + ret = allocate_and_map_gsi_pirq(currd, pirq, &pirq); + if ( ret ) + { + gprintk(XENLOG_WARNING, "vioapic: error mapping GSI %u: %d\n", + gsi, ret); + return ret; + } + + pcidevs_lock(); + ret = pt_irq_create_bind(currd, &pt_irq_bind); + if ( ret ) + { + gprintk(XENLOG_WARNING, "vioapic: error binding GSI %u: %d\n", + gsi, ret); + spin_lock(&currd->event_lock); + unmap_domain_pirq(currd, pirq); + spin_unlock(&currd->event_lock); + } + pcidevs_unlock(); + + return ret; +} + static void vioapic_write_redirent( struct hvm_vioapic *vioapic, unsigned int idx, int top_word, uint32_t val) @@ -190,6 +236,20 @@ static void vioapic_write_redirent( *pent = ent; + if ( is_hardware_domain(d) && unmasked ) + { + int ret; + + ret = vioapic_hwdom_map_gsi(gsi, ent.fields.trig_mode, + ent.fields.polarity); + if ( ret ) + { + /* Mask the entry again. */ + pent->fields.mask = 1; + unmasked = 0; + } + } + if ( gsi == 0 ) { vlapic_adjust_i8259_target(d);