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banners=-,-,- X-VirusChecked: Checked Received: (qmail 24298 invoked from network); 18 Jul 2017 17:17:04 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-16.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 18 Jul 2017 17:17:04 -0000 X-IronPort-AV: E=Sophos;i="5.40,378,1496102400"; d="scan'208";a="431961692" From: Anthony PERARD To: Date: Tue, 18 Jul 2017 18:16:36 +0100 Message-ID: <20170718171637.26038-3-anthony.perard@citrix.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170718171637.26038-1-anthony.perard@citrix.com> References: <20170718171637.26038-1-anthony.perard@citrix.com> MIME-Version: 1.0 Cc: Anthony PERARD , Andrew Cooper Subject: [Xen-devel] [XTF PATCH v2 2/3] vlapic-timer: Test divide register configuration X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Anthony PERARD --- arch/x86/include/arch/apic.h | 3 +++ tests/vlapic-timer/main.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/arch/x86/include/arch/apic.h b/arch/x86/include/arch/apic.h index 4cb262d..0f48df1 100644 --- a/arch/x86/include/arch/apic.h +++ b/arch/x86/include/arch/apic.h @@ -31,6 +31,9 @@ #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 +#define APIC_TDCR 0x3e0 +#define APIC_TDR_DIV_1 0xb +#define APIC_TDR_DIV_16 0x3 #define APIC_DEFAULT_BASE 0xfee00000ul diff --git a/tests/vlapic-timer/main.c b/tests/vlapic-timer/main.c index 47836a8..19f47d7 100644 --- a/tests/vlapic-timer/main.c +++ b/tests/vlapic-timer/main.c @@ -130,6 +130,44 @@ void testing_oneshot_and_periodic_mode(void) xtf_failure("Fail: TMCCT should stay at zero\n"); } +/* + * Testing change of divide configuration + */ +void testing_divide_configuration(void) +{ + uint32_t tmict = 0x49999999; + + printk("Testing change of divide configuration register\n"); + + change_mode(APIC_TIMER_MODE_PERIODIC); + + apic_write(APIC_TDCR, APIC_TDR_DIV_16); + apic_write(APIC_TMICT, tmict); + + wait_until_tmcct_is_half_down(tmict); + + apic_write(APIC_TDCR, APIC_TDR_DIV_1); + + /* + * Checking that changing divide configuration value does not cause the + * current counter register to have a different value, it should continue + * to count down, but at a different rate. + */ + + if ( apic_read(APIC_TMCCT) > (tmict / 2) ) + xtf_failure("Fail: TMCCT may have gone back in time\n"); + if ( apic_read(APIC_TMCCT) == 0 ) + xtf_failure("Fail: TMCCT should not be 0\n"); + + wait_until_tmcct_is_half_down(tmict); + + apic_write(APIC_TDCR, APIC_TDR_DIV_16); + if ( apic_read(APIC_TMCCT) > (tmict / 2) ) + xtf_failure("Fail: TMCCT may have gone back in time\n"); + if ( apic_read(APIC_TMCCT) == 0 ) + xtf_failure("Fail: TMCCT should not be 0\n"); +} + void test_main(void) { if ( apic_init(APIC_MODE_XAPIC) ) @@ -137,6 +175,8 @@ void test_main(void) testing_oneshot_and_periodic_mode(); + testing_divide_configuration(); + xtf_success(NULL); }