From patchwork Fri Jul 21 19:59:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9857601 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 76737601C0 for ; Fri, 21 Jul 2017 20:02:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6912228636 for ; Fri, 21 Jul 2017 20:02:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E35928654; Fri, 21 Jul 2017 20:02:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CDA6828636 for ; Fri, 21 Jul 2017 20:02:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dYe5t-0005BS-Dk; Fri, 21 Jul 2017 20:00:13 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dYe5r-00057Q-JA for xen-devel@lists.xenproject.org; Fri, 21 Jul 2017 20:00:11 +0000 Received: from [85.158.143.35] by server-3.bemta-6.messagelabs.com id 1A/D6-03044-A4D52795; Fri, 21 Jul 2017 20:00:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTdcrtij SYOoqBYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNWPyjC6mgu3iFV0TJBoY3wp2MXJxCAlsZpT4 d30uK4SznFHi0vQ17F2MnBxsAroSO26+ZgaxRQRCJZ4u+A5mMwsoSew/e40RxBYWCJY4uH4vU D0HB4uAqsSq834gYV4BG4mTj/6BlUgIyEk0nL8P1soJFF9x+QkbiC0kYC3RvHgqywRG7gWMDK sYNYpTi8pSi3SNjfWSijLTM0pyEzNzdA0NzPRyU4uLE9NTcxKTivWS83M3MQK9ywAEOxh3rg8 8xCjJwaQkyqtpVRQpxJeUn1KZkVicEV9UmpNafIhRhoNDSYJXPQYoJ1iUmp5akZaZAwwzmLQE B4+SCG8oSJq3uCAxtzgzHSJ1ilGX49WE/9+YhFjy8vNSpcR5Y0CKBECKMkrz4EbAQv4So6yUM C8j0FFCPAWpRbmZJajyrxjFORiVhHnzQabwZOaVwG16BXQEE9ARj9wKQI4oSURISTUw1le+6j CYLHGBc/bJqc80jUpkotbVmO8TP9mvo8256LxP6+ayW9lbr+cmBzmK3VjE27M9g+/QxkI7Nu/ ni8Tn31l1J/NQd7bS/vDLbdKmBg+KuipKHgdxn1FX2a5csdXc6b/hGVWpdZ0rTx68bWIi3NHu vLd7dgTbrkhtp7mWCpMe1Z8uKtRVYinOSDTUYi4qTgQA8Upg93QCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-7.tower-21.messagelabs.com!1500667210!74436548!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9881 invoked from network); 21 Jul 2017 20:00:10 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-7.tower-21.messagelabs.com with SMTP; 21 Jul 2017 20:00:10 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB07C1596; Fri, 21 Jul 2017 13:00:09 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0D0E23F3E1; Fri, 21 Jul 2017 13:00:08 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 21 Jul 2017 20:59:58 +0100 Message-Id: <20170721200010.29010-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170721200010.29010-1-andre.przywara@arm.com> References: <20170721200010.29010-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [RFC PATCH v2 10/22] ARM: vGIC: protect gic_set_lr() with pending_irq lock X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP When putting a (pending) IRQ into an LR, we should better make sure that no-one changes it behind our back. So make sure we take the pending_irq lock. This bubbles up to all users of gic_add_to_lr_pending() and gic_raise_guest_irq(). Signed-off-by: Andre Przywara --- xen/arch/arm/gic.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 8dec736..df89530 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -383,6 +383,7 @@ static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) struct pending_irq *iter; ASSERT(spin_is_locked(&v->arch.vgic.lock)); + ASSERT(spin_is_locked(&n->lock)); if ( !list_empty(&n->lr_queue) ) return; @@ -480,6 +481,7 @@ void gic_update_one_lr(struct vcpu *v, int i) struct pending_irq *p; int irq; struct gic_lr lr_val; + unsigned long flags; ASSERT(spin_is_locked(&v->arch.vgic.lock)); ASSERT(!local_irq_is_enabled()); @@ -534,6 +536,7 @@ void gic_update_one_lr(struct vcpu *v, int i) gic_hw_ops->clear_lr(i); clear_bit(i, &this_cpu(lr_mask)); + vgic_irq_lock(p, flags); if ( p->desc != NULL ) clear_bit(_IRQ_INPROGRESS, &p->desc->status); clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); @@ -559,6 +562,7 @@ void gic_update_one_lr(struct vcpu *v, int i) clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); } } + vgic_irq_unlock(p, flags); } } @@ -592,11 +596,11 @@ static void gic_restore_pending_irqs(struct vcpu *v) int lr = 0; struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; - unsigned long flags; + unsigned long flags, vcpu_flags; unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; int lrs = nr_lrs; - spin_lock_irqsave(&v->arch.vgic.lock, flags); + spin_lock_irqsave(&v->arch.vgic.lock, vcpu_flags); if ( list_empty(&v->arch.vgic.lr_pending) ) goto out; @@ -621,16 +625,20 @@ static void gic_restore_pending_irqs(struct vcpu *v) goto out; found: + vgic_irq_lock(p_r, flags); lr = p_r->lr; p_r->lr = GIC_INVALID_LR; set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); gic_add_to_lr_pending(v, p_r); inflight_r = &p_r->inflight; + vgic_irq_unlock(p_r, flags); } + vgic_irq_lock(p, flags); gic_set_lr(lr, p, GICH_LR_PENDING); list_del_init(&p->lr_queue); + vgic_irq_unlock(p, flags); set_bit(lr, &this_cpu(lr_mask)); /* We can only evict nr_lrs entries */ @@ -640,7 +648,7 @@ found: } out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + spin_unlock_irqrestore(&v->arch.vgic.lock, vcpu_flags); } void gic_clear_pending_irqs(struct vcpu *v)