From patchwork Fri Jul 21 20:00:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9857595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C4884601C0 for ; Fri, 21 Jul 2017 20:02:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B643628636 for ; Fri, 21 Jul 2017 20:02:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AB6222864A; Fri, 21 Jul 2017 20:02:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A48C228636 for ; Fri, 21 Jul 2017 20:02:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dYe65-0005aL-UT; Fri, 21 Jul 2017 20:00:25 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dYe64-0005Rl-2E for xen-devel@lists.xenproject.org; Fri, 21 Jul 2017 20:00:24 +0000 Received: from [85.158.143.35] by server-10.bemta-6.messagelabs.com id E0/DE-03582-75D52795; Fri, 21 Jul 2017 20:00:23 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTTcstij S4NxpG4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNWNN/2Omgvd2Fae2b2ZqYNxn2MXIySEksJlR 4uvayC5GLiB7OaPE+XtvmEASbAK6EjtuvmYGsUUEQiWeLvgOZjMLKEnsP3uNEcQWFnCXeH29j x3EZhFQlbj15D9QDQcHr4CNxLuPYiBhCQE5iYbz98FaOYHCKy4/YYPYay3RvHgqywRG7gWMDK sYNYpTi8pSi3QNzfSSijLTM0pyEzNzdA0NzPRyU4uLE9NTcxKTivWS83M3MQK9ywAEOxjvbww 4xCjJwaQkyqtpVRQpxJeUn1KZkVicEV9UmpNafIhRhoNDSYJ3STRQTrAoNT21Ii0zBxhmMGkJ Dh4lEV6RGKA0b3FBYm5xZjpE6hSjLserCf+/MQmx5OXnpUqJ874DmSEAUpRRmgc3Ahbylxhlp YR5GYGOEuIpSC3KzSxBlX/FKM7BqCTM+xNkCk9mXgncpldARzABHfHIrQDkiJJEhJRUA2Ovk8 bZLrZF1V2H0pP3GVrz//BadPyLdG53E3dQ455c46CKd+XGy1M2617e6ldwKvPa7vrlu5vV1zp 5bziicSxFOtZ+3do9K59NU1z+mWfK0fA1701eTnEKSjJQ7Y8XLnP8+NpoWV3ZhaUVOwuTj5iq KsYzuEVvSa9clXbiyf5b501S+Tq8m5RYijMSDbWYi4oTAbWGg0Z0AgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-3.tower-21.messagelabs.com!1500667222!70915353!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24943 invoked from network); 21 Jul 2017 20:00:22 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-21.messagelabs.com with SMTP; 21 Jul 2017 20:00:22 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2AA251596; Fri, 21 Jul 2017 13:00:22 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F5B53F3E1; Fri, 21 Jul 2017 13:00:21 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Fri, 21 Jul 2017 21:00:10 +0100 Message-Id: <20170721200010.29010-23-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170721200010.29010-1-andre.przywara@arm.com> References: <20170721200010.29010-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [RFC PATCH v2 22/22] ARM: vGIC: remove remaining irq_rank code X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Now that we no longer need the struct vgic_irq_rank, we can remove the definition and all the helper functions. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic.c | 54 -------------------------------------------- xen/include/asm-arm/domain.h | 6 +---- xen/include/asm-arm/vgic.h | 48 --------------------------------------- 3 files changed, 1 insertion(+), 107 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index dd969e2..8ce3ce5 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -32,35 +32,6 @@ #include #include -static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v, int rank) -{ - if ( rank == 0 ) - return v->arch.vgic.private_irqs; - else if ( rank <= DOMAIN_NR_RANKS(v->domain) ) - return &v->domain->arch.vgic.shared_irqs[rank - 1]; - else - return NULL; -} - -/* - * Returns rank corresponding to a GICD_ register for - * GICD_ with -bits-per-interrupt. - */ -struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, - int s) -{ - int rank = REG_RANK_NR(b, (n >> s)); - - return vgic_get_rank(v, rank); -} - -struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq) -{ - int rank = irq/32; - - return vgic_get_rank(v, rank); -} - void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq, unsigned int vcpu_id) { @@ -75,14 +46,6 @@ void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq, p->vcpu_id = vcpu_id; } -static void vgic_rank_init(struct vgic_irq_rank *rank, uint8_t index, - unsigned int vcpu) -{ - spin_lock_init(&rank->lock); - - rank->index = index; -} - int domain_vgic_register(struct domain *d, int *mmio_count) { switch ( d->arch.vgic.version ) @@ -121,11 +84,6 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis) spin_lock_init(&d->arch.vgic.lock); - d->arch.vgic.shared_irqs = - xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_RANKS(d)); - if ( d->arch.vgic.shared_irqs == NULL ) - return -ENOMEM; - d->arch.vgic.pending_irqs = xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis); if ( d->arch.vgic.pending_irqs == NULL ) @@ -134,9 +92,6 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis) /* SPIs are routed to VCPU0 by default */ for (i=0; iarch.vgic.nr_spis; i++) vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i], i + 32, 0); - /* SPIs are routed to VCPU0 by default */ - for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ ) - vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0); ret = d->arch.vgic.handler->domain_init(d); if ( ret ) @@ -178,7 +133,6 @@ void domain_vgic_free(struct domain *d) } d->arch.vgic.handler->domain_free(d); - xfree(d->arch.vgic.shared_irqs); xfree(d->arch.vgic.pending_irqs); xfree(d->arch.vgic.allocated_irqs); } @@ -187,13 +141,6 @@ int vcpu_vgic_init(struct vcpu *v) { int i; - v->arch.vgic.private_irqs = xzalloc(struct vgic_irq_rank); - if ( v->arch.vgic.private_irqs == NULL ) - return -ENOMEM; - - /* SGIs/PPIs are always routed to this VCPU */ - vgic_rank_init(v->arch.vgic.private_irqs, 0, v->vcpu_id); - v->domain->arch.vgic.handler->vcpu_init(v); memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs)); @@ -210,7 +157,6 @@ int vcpu_vgic_init(struct vcpu *v) int vcpu_vgic_free(struct vcpu *v) { - xfree(v->arch.vgic.private_irqs); return 0; } diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 8dfc1d1..418400f 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -83,15 +83,12 @@ struct arch_domain * shared_irqs where each member contains its own locking. * * If both class of lock is required then this lock must be - * taken first. If multiple rank locks are required (including - * the per-vcpu private_irqs rank) then they must be taken in - * rank order. + * taken first. */ spinlock_t lock; uint32_t ctlr; int nr_spis; /* Number of SPIs */ unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ - struct vgic_irq_rank *shared_irqs; /* * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in * struct arch_vcpu. @@ -248,7 +245,6 @@ struct arch_vcpu * struct arch_domain. */ struct pending_irq pending_irqs[32]; - struct vgic_irq_rank *private_irqs; /* This list is ordered by IRQ priority and it is used to keep * track of the IRQs that the VGIC injected into the guest. diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 233ff1f..9c79c5e 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -101,16 +101,6 @@ struct pending_irq spinlock_t lock; }; -#define NR_INTERRUPT_PER_RANK 32 -#define INTERRUPT_RANK_MASK (NR_INTERRUPT_PER_RANK - 1) - -/* Represents state corresponding to a block of 32 interrupts */ -struct vgic_irq_rank { - spinlock_t lock; /* Covers access to all other members of this struct */ - - uint8_t index; -}; - struct sgi_target { uint8_t aff1; uint16_t list; @@ -137,42 +127,12 @@ struct vgic_ops { const unsigned int max_vcpus; }; -/* Number of ranks of interrupt registers for a domain */ -#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32) - #define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock) #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock) #define vgic_irq_lock(p, flags) spin_lock_irqsave(&(p)->lock, flags) #define vgic_irq_unlock(p, flags) spin_unlock_irqrestore(&(p)->lock, flags) -#define vgic_lock_rank(v, r, flags) spin_lock_irqsave(&(r)->lock, flags) -#define vgic_unlock_rank(v, r, flags) spin_unlock_irqrestore(&(r)->lock, flags) - -/* - * Rank containing GICD_ for GICD_ with - * -bits-per-interrupt - */ -static inline int REG_RANK_NR(int b, uint32_t n) -{ - switch ( b ) - { - /* - * IRQ ranks are of size 32. So n cannot be shifted beyond 5 for 32 - * and above. For 64-bit n is already shifted DBAT_DOUBLE_WORD - * by the caller - */ - case 64: - case 32: return n >> 5; - case 16: return n >> 4; - case 8: return n >> 3; - case 4: return n >> 2; - case 2: return n >> 1; - case 1: return n; - default: BUG(); - } -} - void vgic_lock_irqs(struct vcpu *v, unsigned int nrirqs, unsigned int first_irq, struct pending_irq **pirqs); void vgic_unlock_irqs(struct pending_irq **pirqs, unsigned int nrirqs); @@ -193,12 +153,6 @@ void vgic_store_irq_disable(struct vcpu *v, unsigned int first_irq, enum gic_sgi_mode; /* - * Offset of GICD_ with its rank, for GICD_ size with - * -bits-per-interrupt. - */ -#define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32) - -/* * In the moment vgic_num_irqs() just covers SPIs and the private IRQs, * as it's mostly used for allocating the pending_irq and irq_desc array, * in which LPIs don't participate. @@ -217,8 +171,6 @@ extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq, unsigned int vcpu_id); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); extern struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq); -extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s); -extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq); extern bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count);