From patchwork Wed Aug 30 10:34:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Dyasli X-Patchwork-Id: 9929273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5545B60309 for ; Wed, 30 Aug 2017 10:37:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E9B72843B for ; Wed, 30 Aug 2017 10:37:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 536E22847B; Wed, 30 Aug 2017 10:37:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CFF1C2843B for ; Wed, 30 Aug 2017 10:37:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dn0KZ-000113-EK; Wed, 30 Aug 2017 10:34:43 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dn0KX-000108-SS for xen-devel@lists.xen.org; Wed, 30 Aug 2017 10:34:41 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id 0C/CB-01778-1C496A95; Wed, 30 Aug 2017 10:34:41 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeJIrShJLcpLzFFi42JxWrohUvfAlGW RBocfyVos+biYxYHR4+ju30wBjFGsmXlJ+RUJrBn3vz5nLliqU7HmYUoD4w3lLkZODgkBf4kn yzewgdhsAnoSG2e/YgKxRQRkJVZ3zWHvYuTiYBbYwiwxr/M5cxcjB4ewQLDEzQe2IDUsAqoSB x4sYgcJ8wrYSKz4ZgYxUl5iV9tFVhCbU8BW4tjvg4wgthBQSf/rBewQtqrE6xe7WEBsXgFBiZ Mzn4DZzAISEgdfvGCewMg7C0lqFpLUAkamVYwaxalFZalFukZGeklFmekZJbmJmTm6hgbGerm pxcWJ6ak5iUnFesn5uZsYgYFTz8DAuINx6gm/Q4ySHExKorwxk5ZFCvEl5adUZiQWZ8QXleak Fh9ilOHgUJLg3TYRKCdYlJqeWpGWmQMMYZi0BAePkgjvPZBW3uKCxNzizHSI1ClGRSlx3rLJQ AkBkERGaR5cGyxuLjHKSgnzMjIwMAjxFKQW5WaWoMq/YhTnYFQS5s0FmcKTmVcCN/0V0GImoM WxXktBFpckIqSkGhhZ+GwM/b+dnDXjtMinva/n7J0T6VK8+HHazch77sV/DCPqlLZ8Fgn4cOv 8Ie7Ftb0hWzz//PFy0bm4aGNH8okZC6S4vmi6euvGvvipuVlsv/y9vzufONmVf6vOKSlk21Lw Ku+mOrtPJCNnzT6XFYKR8TNW7Hjz64I6a8SPzfnHLvclLlnrLnxaiaU4I9FQi7moOBEAsn7lq pYCAAA= X-Env-Sender: prvs=408f3fb1e=sergey.dyasli@citrix.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1504089278!104672979!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 52288 invoked from network); 30 Aug 2017 10:34:40 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-16.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 30 Aug 2017 10:34:40 -0000 X-IronPort-AV: E=Sophos;i="5.41,448,1498521600"; d="scan'208";a="437433973" From: Sergey Dyasli To: Date: Wed, 30 Aug 2017 11:34:31 +0100 Message-ID: <20170830103433.6605-4-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170830103433.6605-1-sergey.dyasli@citrix.com> References: <20170830103433.6605-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Cc: Sergey Dyasli , Kevin Tian , Stefano Stabellini , Wei Liu , Jun Nakajima , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Jan Beulich Subject: [Xen-devel] [PATCH v1 3/5] x86: replace arch_vcpu::cpuid_faulting with msr_vcpu_policy X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Since each vCPU now has struct msr_vcpu_policy, use cpuid_faulting bit from there in current logic and remove arch_vcpu::cpuid_faulting. Signed-off-by: Sergey Dyasli Reviewed-by: Kevin Tian --- xen/arch/x86/cpu/intel.c | 3 ++- xen/arch/x86/hvm/hvm.c | 4 +++- xen/arch/x86/hvm/vmx/vmx.c | 10 ++++++---- xen/arch/x86/pv/emul-inv-op.c | 4 +++- xen/arch/x86/pv/emul-priv-op.c | 5 +++-- xen/include/asm-x86/domain.h | 3 --- 6 files changed, 17 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 2e20327569..487eb06148 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -156,6 +156,7 @@ static void intel_ctxt_switch_levelling(const struct vcpu *next) struct cpuidmasks *these_masks = &this_cpu(cpuidmasks); const struct domain *nextd = next ? next->domain : NULL; const struct cpuidmasks *masks; + const struct msr_vcpu_policy *vp = next->arch.msr; if (cpu_has_cpuid_faulting) { /* @@ -176,7 +177,7 @@ static void intel_ctxt_switch_levelling(const struct vcpu *next) */ set_cpuid_faulting(nextd && !is_control_domain(nextd) && (is_pv_domain(nextd) || - next->arch.cpuid_faulting)); + vp->misc_features_enables.cpuid_faulting)); return; } diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 6cb903def5..2ad07d52bc 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3286,7 +3286,9 @@ unsigned long copy_from_user_hvm(void *to, const void *from, unsigned len) bool hvm_check_cpuid_faulting(struct vcpu *v) { - if ( !v->arch.cpuid_faulting ) + const struct msr_vcpu_policy *vp = v->arch.msr; + + if ( !vp->misc_features_enables.cpuid_faulting ) return false; return hvm_get_cpl(v) > 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 67fc85b201..155fba9017 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2902,7 +2902,7 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) case MSR_INTEL_MISC_FEATURES_ENABLES: *msr_content = 0; - if ( current->arch.cpuid_faulting ) + if ( current->arch.msr->misc_features_enables.cpuid_faulting ) *msr_content |= MSR_MISC_FEATURES_CPUID_FAULTING; break; @@ -3134,15 +3134,17 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) case MSR_INTEL_MISC_FEATURES_ENABLES: { - bool old_cpuid_faulting = v->arch.cpuid_faulting; + struct msr_vcpu_policy *vp = v->arch.msr; + bool old_cpuid_faulting = vp->misc_features_enables.cpuid_faulting; if ( msr_content & ~MSR_MISC_FEATURES_CPUID_FAULTING ) goto gp_fault; - v->arch.cpuid_faulting = msr_content & MSR_MISC_FEATURES_CPUID_FAULTING; + vp->misc_features_enables.cpuid_faulting = + msr_content & MSR_MISC_FEATURES_CPUID_FAULTING; if ( cpu_has_cpuid_faulting && - (old_cpuid_faulting ^ v->arch.cpuid_faulting) ) + (old_cpuid_faulting ^ vp->misc_features_enables.cpuid_faulting) ) ctxt_switch_levelling(v); break; } diff --git a/xen/arch/x86/pv/emul-inv-op.c b/xen/arch/x86/pv/emul-inv-op.c index 415d294c53..f8944170d5 100644 --- a/xen/arch/x86/pv/emul-inv-op.c +++ b/xen/arch/x86/pv/emul-inv-op.c @@ -66,6 +66,7 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs) char sig[5], instr[2]; unsigned long eip, rc; struct cpuid_leaf res; + const struct msr_vcpu_policy *vp = current->arch.msr; eip = regs->rip; @@ -89,7 +90,8 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs) return 0; /* If cpuid faulting is enabled and CPL>0 inject a #GP in place of #UD. */ - if ( current->arch.cpuid_faulting && !guest_kernel_mode(current, regs) ) + if ( vp->misc_features_enables.cpuid_faulting && + !guest_kernel_mode(current, regs) ) { regs->rip = eip; pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index d50f51944f..66cda538fc 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -948,7 +948,7 @@ static int priv_op_read_msr(unsigned int reg, uint64_t *val, rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, *val) ) break; *val = 0; - if ( curr->arch.cpuid_faulting ) + if ( curr->arch.msr->misc_features_enables.cpuid_faulting ) *val |= MSR_MISC_FEATURES_CPUID_FAULTING; return X86EMUL_OKAY; @@ -1154,7 +1154,8 @@ static int priv_op_write_msr(unsigned int reg, uint64_t val, if ( (val & MSR_MISC_FEATURES_CPUID_FAULTING) && !this_cpu(cpuid_faulting_enabled) ) break; - curr->arch.cpuid_faulting = !!(val & MSR_MISC_FEATURES_CPUID_FAULTING); + curr->arch.msr->misc_features_enables.cpuid_faulting = + !!(val & MSR_MISC_FEATURES_CPUID_FAULTING); return X86EMUL_OKAY; case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7): diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domain.h index 866a03b508..60c02650d5 100644 --- a/xen/include/asm-x86/domain.h +++ b/xen/include/asm-x86/domain.h @@ -555,9 +555,6 @@ struct arch_vcpu * and thus should be saved/restored. */ bool_t nonlazy_xstate_used; - /* Has the guest enabled CPUID faulting? */ - bool cpuid_faulting; - /* * The SMAP check policy when updating runstate_guest(v) and the * secondary system time.