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Wed, 11 Oct 2017 07:15:39 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id q206sm7881306qke.54.2017.10.11.07.15.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Oct 2017 07:15:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 11 Oct 2017 15:15:33 +0100 Message-Id: <20171011141533.11231-1-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 Cc: andre.przywara@arm.com, sstabellini@kernel.org, Julien Grall Subject: [Xen-devel] [PATCH for-4.10] xen/arm: mm: Rework MAIR* definitions to handle 32-bit compilation environment X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Commit a0543df403 "xen/arm: page: Clean-up the definition of MAIRVAL" combined the definition of MAIR0VAL and MAIR1VAL in MAIRVAL. Sadly, when building in 32-bit environment, the assembler is unable to compute 64-bit constant and will ignore the 32-bit most-significants bits. This will result of MAIR1 set 0. Rather than fully reverting the offending commit, the code is reworked to still avoid hardcoded values but split the definition in 2. Lastly, a comment is added to avoid trying to blindly combine the both definition again in the future. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/include/asm-arm/page.h | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index f558184e10..d948250a4a 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -52,18 +52,23 @@ * ?? 101 * reserved 110 * MT_NORMAL 111 1111 1111 -- Write-back write-allocate + * + * /!\ It is not possible to combine the definition in MAIRVAL and then + * split because it would result to a 64-bit value that some assembler + * doesn't understand. */ -#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8)) +#define _MAIR0(attr, mt) (_AC(attr, ULL) << ((mt) * 8)) +#define _MAIR1(attr, mt) (_AC(attr, ULL) << (((mt) * 8) - 32)) + +#define MAIR0VAL (_MAIR0(0x00, MT_DEVICE_nGnRnE)| \ + _MAIR0(0x44, MT_NORMAL_NC) | \ + _MAIR0(0xaa, MT_NORMAL_WT) | \ + _MAIR0(0xee, MT_NORMAL_WB)) -#define MAIRVAL (MAIR(0x00, MT_DEVICE_nGnRnE)| \ - MAIR(0x44, MT_NORMAL_NC) | \ - MAIR(0xaa, MT_NORMAL_WT) | \ - MAIR(0xee, MT_NORMAL_WB) | \ - MAIR(0x04, MT_DEVICE_nGnRE) | \ - MAIR(0xff, MT_NORMAL)) +#define MAIR1VAL (_MAIR1(0x04, MT_DEVICE_nGnRE) | \ + _MAIR1(0xff, MT_NORMAL)) -#define MAIR0VAL (MAIRVAL & 0xffffffff) -#define MAIR1VAL (MAIRVAL >> 32) +#define MAIRVAL (MAIR1VAL << 32 | MAIR0VAL) /* * Layout of the flags used for updating the hypervisor page tables