From patchwork Tue Oct 17 13:24:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Durrant X-Patchwork-Id: 10012025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 224D560235 for ; Tue, 17 Oct 2017 13:27:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17BE02884B for ; Tue, 17 Oct 2017 13:27:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0BE9E288B9; Tue, 17 Oct 2017 13:27:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D2CF2884B for ; Tue, 17 Oct 2017 13:27:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4Rra-0000LH-QN; Tue, 17 Oct 2017 13:24:54 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4RrZ-0000Ju-KJ for xen-devel@lists.xenproject.org; Tue, 17 Oct 2017 13:24:53 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 7A/08-24473-4A406E95; Tue, 17 Oct 2017 13:24:52 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRWlGSWpSXmKPExsXitHSDve48lme RBidui1p83zKZyYHR4/CHKywBjFGsmXlJ+RUJrBmvDl5jLvipXfGwdx1bA2OrQhcjJ4eEgL/E zYXXmUBsNgEdialPL7F2MXJwiAioSNzea9DFyMXBLHCUSeLo7GdsIDXCAsESa37PArNZBFQl5 u59zQpi8wrYSGx9/4UNYqa8xK62i2BxTgFbidf/DjCD2EJANZvmrWeFsFUk1k+FmMMrIChxcu YTFhCbWUBC4uCLF8wTGHlnIUnNQpJawMi0ilG9OLWoLLVI11QvqSgzPaMkNzEzR9fQwFgvN7W 4ODE9NScxqVgvOT93EyMwdOoZGBh3MF7+6nSIUZKDSUmU19nwSaQQX1J+SmVGYnFGfFFpTmrx IUYZDg4lCd5g5meRQoJFqempFWmZOcAghklLcPAoifBmgKR5iwsSc4sz0yFSpxh1OTpu3v3DJ MSSl5+XKiXOKwhSJABSlFGaBzcCFlGXGGWlhHkZGRgYhHgKUotyM0tQ5V8xinMwKgnzGoBM4c nMK4Hb9AroCCagI9Y5PQE5oiQRISXVwKjcYxzny2wauPPKMhW+CXuLdstXJ5zNeBb++mPu1cc MD4S/JgSv3Fa7dfs+s/mLG5c0is2+Uj9rieihiO3szoqrbmWKRR27eGJ3TmXGgtNX2b9bWBgJ f/UIms+w/Ivie209Dp3LM2IvzG08wRzGzr1i/+78xDI9f95lVxZnhGSdadu3M+3Uf2klluKMR EMt5qLiRAAOiogrowIAAA== X-Env-Sender: prvs=4567f63fb=Paul.Durrant@citrix.com X-Msg-Ref: server-8.tower-31.messagelabs.com!1508246683!110724835!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 55220 invoked from network); 17 Oct 2017 13:24:46 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-8.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 17 Oct 2017 13:24:46 -0000 X-IronPort-AV: E=Sophos;i="5.43,391,1503360000"; d="scan'208";a="454570836" From: Paul Durrant To: Date: Tue, 17 Oct 2017 14:24:28 +0100 Message-ID: <20171017132432.24093-8-paul.durrant@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171017132432.24093-1-paul.durrant@citrix.com> References: <20171017132432.24093-1-paul.durrant@citrix.com> MIME-Version: 1.0 Cc: Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Paul Durrant Subject: [Xen-devel] [PATCH v12 07/11] x86/mm: add an extra command to HYPERVISOR_mmu_update... X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP ...to allow the calling domain to prevent translation of specified l1e value. Despite what the comment in public/xen.h might imply, specifying a command value of MMU_NORMAL_PT_UPDATE will not simply update an l1e with the specified value. Instead, mod_l1_entry() tests whether foreign_dom has PG_translate set in its paging mode and, if it does, assumes that the the pfn value in the l1e is a gfn rather than an mfn. To allow PV tools domain to map mfn values from a previously issued HYPERVISOR_memory_op:XENMEM_acquire_resource, there needs to be a way to tell HYPERVISOR_mmu_update that the specific l1e value does not require translation regardless of the paging mode of foreign_dom. This patch therefore defines a new command value, MMU_PT_UPDATE_NO_TRANSLATE, which has the same semantics as MMU_NORMAL_PT_UPDATE except that the paging mode of foreign_dom is ignored and the l1e value is used verbatim. Signed-off-by: Paul Durrant Reviewed-by: Jan Beulich --- Cc: Andrew Cooper Cc: George Dunlap Cc: Ian Jackson Cc: Konrad Rzeszutek Wilk Cc: Stefano Stabellini Cc: Tim Deegan Cc: Wei Liu v8: - New in this version, replacing "allow a privileged PV domain to map guest mfns". --- xen/arch/x86/mm.c | 17 ++++++++++------- xen/include/public/xen.h | 12 +++++++++--- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 1d15ae2a15..63539d5d0b 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -1619,9 +1619,10 @@ void page_unlock(struct page_info *page) /* Update the L1 entry at pl1e to new value nl1e. */ static int mod_l1_entry(l1_pgentry_t *pl1e, l1_pgentry_t nl1e, - unsigned long gl1mfn, int preserve_ad, + unsigned long gl1mfn, unsigned int cmd, struct vcpu *pt_vcpu, struct domain *pg_dom) { + bool preserve_ad = (cmd == MMU_PT_UPDATE_PRESERVE_AD); l1_pgentry_t ol1e; struct domain *pt_dom = pt_vcpu->domain; int rc = 0; @@ -1643,7 +1644,8 @@ static int mod_l1_entry(l1_pgentry_t *pl1e, l1_pgentry_t nl1e, return -EINVAL; } - if ( paging_mode_translate(pg_dom) ) + if ( cmd != MMU_PT_UPDATE_NO_TRANSLATE && + paging_mode_translate(pg_dom) ) { page = get_page_from_gfn(pg_dom, l1e_get_pfn(nl1e), NULL, P2M_ALLOC); if ( !page ) @@ -3258,6 +3260,7 @@ long do_mmu_update( */ case MMU_NORMAL_PT_UPDATE: case MMU_PT_UPDATE_PRESERVE_AD: + case MMU_PT_UPDATE_NO_TRANSLATE: { p2m_type_t p2mt; @@ -3323,7 +3326,8 @@ long do_mmu_update( p2m_query_t q = (l1e_get_flags(l1e) & _PAGE_RW) ? P2M_UNSHARE : P2M_ALLOC; - if ( paging_mode_translate(pg_owner) ) + if ( cmd != MMU_PT_UPDATE_NO_TRANSLATE && + paging_mode_translate(pg_owner) ) target = get_page_from_gfn(pg_owner, l1e_get_pfn(l1e), &l1e_p2mt, q); @@ -3350,9 +3354,7 @@ long do_mmu_update( break; } - rc = mod_l1_entry(va, l1e, mfn, - cmd == MMU_PT_UPDATE_PRESERVE_AD, v, - pg_owner); + rc = mod_l1_entry(va, l1e, mfn, cmd, v, pg_owner); if ( target ) put_page(target); } @@ -3630,7 +3632,8 @@ static int __do_update_va_mapping( goto out; } - rc = mod_l1_entry(pl1e, val, mfn_x(gl1mfn), 0, v, pg_owner); + rc = mod_l1_entry(pl1e, val, mfn_x(gl1mfn), MMU_NORMAL_PT_UPDATE, v, + pg_owner); page_unlock(gl1pg); put_page(gl1pg); diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index 2ac6b1e24d..d2014a39eb 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -268,6 +268,10 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed * with those in @val. * + * ptr[1:0] == MMU_PT_UPDATE_NO_TRANSLATE: + * As MMU_NORMAL_PT_UPDATE above, but @val is not translated though FD + * page tables. + * * @val is usually the machine frame number along with some attributes. * The attributes by default follow the architecture defined bits. Meaning that * if this is a X86_64 machine and four page table layout is used, the layout @@ -334,9 +338,11 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. */ -#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ -#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ -#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ +#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ +#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ +#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ +#define MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. prt is MA. */ + /* val never translated. */ /* * MMU EXTENDED OPERATIONS