From patchwork Wed Oct 18 08:27:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Dyasli X-Patchwork-Id: 10014085 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9357560215 for ; Wed, 18 Oct 2017 08:30:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8040328AAE for ; Wed, 18 Oct 2017 08:30:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 74EBC28AF8; Wed, 18 Oct 2017 08:30:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AB8F328AF2 for ; Wed, 18 Oct 2017 08:30:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4jhe-0002ab-Lt; Wed, 18 Oct 2017 08:27:50 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4jhc-0002a8-Lr for xen-devel@lists.xen.org; Wed, 18 Oct 2017 08:27:48 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id 70/E8-18968-38017E95; Wed, 18 Oct 2017 08:27:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRWlGSWpSXmKPExsXitHSDvW6zwPN Ig11z+C2WfFzM4sDocXT3b6YAxijWzLyk/IoE1owFK/6yFkzoYay4NvUuawPjpcAuRg4OCQF/ iRnLoroYOTnYBPQkNs5+xQRiiwjISqzumsPexcjFwSxwhFFi6qoj7CAJYQFviTuLnoPZLAKqE svvTWQEsXkFbCR2/ZjMBmJLCMhL7Gq7yApicwrYSlw/vQYsLgRU8/vNVVYIW1Xi9YtdLBC9gh InZz4Bs5kFJCQOvnjBPIGRdxaS1CwkqQWMTKsY1YtTi8pSi3Qt9ZKKMtMzSnITM3N0DQ2M9XJ Ti4sT01NzEpOK9ZLzczcxAoOnnoGBcQfj659OhxglOZiURHl1DzyLFOJLyk+pzEgszogvKs1J LT7EKMPBoSTBu4r/eaSQYFFqempFWmYOMIxh0hIcPEoivIEgad7igsTc4sx0iNQpRl2Ojpt3/ zAJseTl56VKifNWgBQJgBRllObBjYDF1CVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrwNIF N4MvNK4Da9AjqCCeiIdU5PQI4oSURISTUwTr0vuupCo3Fdss5jrtUTdzzZs/NPhG+nxIP2O3s N5OVntq3Kzlol2fmtd7as1Trvqxmbm7eybCj5v2n1Y527cW5PN8/ceLI6KGN9lSpHio/jmdX7 t70+z3A1dZOW04aoU4caV7m7rY11Xvtpu8P85d+vt8w8KX7JfcGNb88NpymttMpcouSe90WJp Tgj0VCLuag4EQBewuPKpAIAAA== X-Env-Sender: prvs=457a530fd=sergey.dyasli@citrix.com X-Msg-Ref: server-15.tower-31.messagelabs.com!1508315263!106734118!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36053 invoked from network); 18 Oct 2017 08:27:46 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-15.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 18 Oct 2017 08:27:46 -0000 X-IronPort-AV: E=Sophos;i="5.43,395,1503360000"; d="scan'208";a="454748842" From: Sergey Dyasli To: Date: Wed, 18 Oct 2017 09:27:17 +0100 Message-ID: <20171018082722.6279-3-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171018082722.6279-1-sergey.dyasli@citrix.com> References: <20171018082722.6279-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Kevin Tian , Jan Beulich , Jun Nakajima , Sergey Dyasli Subject: [Xen-devel] [PATCH v4 2/7] x86/msr: add VMX MSRs into struct msr_domain_policy X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP New definitions provide a convenient way of accessing contents of VMX MSRs. They are separated into 5 logical blocks: 1. vmx: [VMX_BASIC, VMX_VMCS_ENUM] 2. VMX_PROCBASED_CTLS2 3. VMX_EPT_VPID_CAP 4. vmx_true_ctls: [VMX_TRUE_PINBASED_CTLS, VMX_TRUE_ENTRY_CTLS] 5. VMX_VMFUNC Every bit value is accessible by its name and bit names match existing Xen's definitions as close as possible. There is a "raw" 64-bit field for each MSR as well as "raw" arrays for vmx and vmx_true_ctls blocks. Signed-off-by: Sergey Dyasli --- xen/arch/x86/msr.c | 63 ++++++++ xen/include/asm-x86/msr.h | 373 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 436 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9737ed706e..9dc3de8ce1 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -216,6 +216,69 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) return X86EMUL_EXCEPTION; } +static void __init __maybe_unused build_assertions(void) +{ + struct msr_domain_policy dp; + + BUILD_BUG_ON(sizeof(dp.vmx.basic) != + sizeof(dp.vmx.basic.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.pinbased_ctls) != + sizeof(dp.vmx.pinbased_ctls.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.procbased_ctls) != + sizeof(dp.vmx.procbased_ctls.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.exit_ctls) != + sizeof(dp.vmx.exit_ctls.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.entry_ctls) != + sizeof(dp.vmx.entry_ctls.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.misc) != + sizeof(dp.vmx.misc.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.cr0_fixed0) != + sizeof(dp.vmx.cr0_fixed0.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.cr0_fixed1) != + sizeof(dp.vmx.cr0_fixed1.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.cr4_fixed0) != + sizeof(dp.vmx.cr4_fixed0.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.cr4_fixed1) != + sizeof(dp.vmx.cr4_fixed1.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.vmcs_enum) != + sizeof(dp.vmx.vmcs_enum.raw)); + BUILD_BUG_ON(sizeof(dp.vmx.raw) != + sizeof(dp.vmx.basic) + + sizeof(dp.vmx.pinbased_ctls) + + sizeof(dp.vmx.procbased_ctls) + + sizeof(dp.vmx.exit_ctls) + + sizeof(dp.vmx.entry_ctls) + + sizeof(dp.vmx.misc) + + sizeof(dp.vmx.cr0_fixed0) + + sizeof(dp.vmx.cr0_fixed1) + + sizeof(dp.vmx.cr4_fixed0) + + sizeof(dp.vmx.cr4_fixed1) + + sizeof(dp.vmx.vmcs_enum)); + + BUILD_BUG_ON(sizeof(dp.vmx_procbased_ctls2) != + sizeof(dp.vmx_procbased_ctls2.raw)); + + BUILD_BUG_ON(sizeof(dp.vmx_ept_vpid_cap) != + sizeof(dp.vmx_ept_vpid_cap.raw)); + + BUILD_BUG_ON(sizeof(dp.vmx_true_ctls.pinbased) != + sizeof(dp.vmx_true_ctls.pinbased.raw)); + BUILD_BUG_ON(sizeof(dp.vmx_true_ctls.procbased) != + sizeof(dp.vmx_true_ctls.procbased.raw)); + BUILD_BUG_ON(sizeof(dp.vmx_true_ctls.exit) != + sizeof(dp.vmx_true_ctls.exit.raw)); + BUILD_BUG_ON(sizeof(dp.vmx_true_ctls.entry) != + sizeof(dp.vmx_true_ctls.entry.raw)); + BUILD_BUG_ON(sizeof(dp.vmx_true_ctls.raw) != + sizeof(dp.vmx_true_ctls.pinbased) + + sizeof(dp.vmx_true_ctls.procbased) + + sizeof(dp.vmx_true_ctls.exit) + + sizeof(dp.vmx_true_ctls.entry)); + + BUILD_BUG_ON(sizeof(dp.vmx_vmfunc) != + sizeof(dp.vmx_vmfunc.raw)); +} + /* * Local variables: * mode: C diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h index 751fa25a36..150000551f 100644 --- a/xen/include/asm-x86/msr.h +++ b/xen/include/asm-x86/msr.h @@ -202,6 +202,171 @@ void write_efer(u64 val); DECLARE_PER_CPU(u32, ler_msr); +union vmx_pin_based_exec_control_bits { + uint32_t raw; + struct { + bool ext_intr_exiting:1; + uint32_t :2; /* 1:2 reserved */ + bool nmi_exiting:1; + uint32_t :1; /* 4 reserved */ + bool virtual_nmis:1; + bool preempt_timer:1; + bool posted_interrupt:1; + uint32_t :24; /* 8:31 reserved */ + }; +}; + +union vmx_cpu_based_exec_control_bits { + uint32_t raw; + struct { + uint32_t :2; /* 0:1 reserved */ + bool virtual_intr_pending:1; + bool use_tsc_offseting:1; + uint32_t :3; /* 4:6 reserved */ + bool hlt_exiting:1; + uint32_t :1; /* 8 reserved */ + bool invlpg_exiting:1; + bool mwait_exiting:1; + bool rdpmc_exiting:1; + bool rdtsc_exiting:1; + uint32_t :2; /* 13:14 reserved */ + bool cr3_load_exiting:1; + bool cr3_store_exiting:1; + uint32_t :2; /* 17:18 reserved */ + bool cr8_load_exiting:1; + bool cr8_store_exiting:1; + bool tpr_shadow:1; + bool virtual_nmi_pending:1; + bool mov_dr_exiting:1; + bool uncond_io_exiting:1; + bool activate_io_bitmap:1; + uint32_t :1; /* 26 reserved */ + bool monitor_trap_flag:1; + bool activate_msr_bitmap:1; + bool monitor_exiting:1; + bool pause_exiting:1; + bool activate_secondary_controls:1; + }; +}; + +union vmx_vmexit_control_bits { + uint32_t raw; + struct { + uint32_t :2; /* 0:1 reserved */ + bool save_debug_cntrls:1; + uint32_t :6; /* 3:8 reserved */ + bool ia32e_mode:1; + uint32_t :2; /* 10:11 reserved */ + bool load_perf_global_ctrl:1; + uint32_t :2; /* 13:14 reserved */ + bool ack_intr_on_exit:1; + uint32_t :2; /* 16:17 reserved */ + bool save_guest_pat:1; + bool load_host_pat:1; + bool save_guest_efer:1; + bool load_host_efer:1; + bool save_preempt_timer:1; + bool clear_bndcfgs:1; + bool conceal_vmexits_from_pt:1; + uint32_t :7; /* 25:31 reserved */ + }; +}; + +union vmx_vmentry_control_bits { + uint32_t raw; + struct { + uint32_t :2; /* 0:1 reserved */ + bool load_debug_cntrls:1; + uint32_t :6; /* 3:8 reserved */ + bool ia32e_mode:1; + bool smm:1; + bool deact_dual_monitor:1; + uint32_t :1; /* 12 reserved */ + bool load_perf_global_ctrl:1; + bool load_guest_pat:1; + bool load_guest_efer:1; + bool load_bndcfgs:1; + bool conceal_vmentries_from_pt:1; + uint32_t :14; /* 18:31 reserved */ + }; +}; + +union vmx_secondary_exec_control_bits { + uint32_t raw; + struct { + bool virtualize_apic_accesses:1; + bool enable_ept:1; + bool descriptor_table_exiting:1; + bool enable_rdtscp:1; + bool virtualize_x2apic_mode:1; + bool enable_vpid:1; + bool wbinvd_exiting:1; + bool unrestricted_guest:1; + bool apic_register_virt:1; + bool virtual_intr_delivery:1; + bool pause_loop_exiting:1; + bool rdrand_exiting:1; + bool enable_invpcid:1; + bool enable_vm_functions:1; + bool enable_vmcs_shadowing:1; + bool encls_exiting:1; + bool rdseed_exiting:1; + bool enable_pml:1; + bool enable_virt_exceptions:1; + bool conceal_vmx_nonroot_from_pt:1; + bool xsaves:1; + uint32_t :1; /* 21 reserved */ + bool ept_mode_based_exec_cntrl:1; + uint32_t :2; /* 23:24 reserved */ + bool tsc_scaling:1; + uint32_t :6; /* 26:31 reserved */ + }; +}; + +struct cr0_bits { + bool pe:1; + bool mp:1; + bool em:1; + bool ts:1; + bool et:1; + bool ne:1; + uint32_t :10; /* 6:15 reserved */ + bool wp:1; + uint32_t :1; /* 17 reserved */ + bool am:1; + uint32_t :10; /* 19:28 reserved */ + bool nw:1; + bool cd:1; + bool pg:1; +}; + +struct cr4_bits { + bool vme:1; + bool pvi:1; + bool tsd:1; + bool de:1; + bool pse:1; + bool pae:1; + bool mce:1; + bool pge:1; + bool pce:1; + bool osfxsr:1; + bool osxmmexcpt:1; + bool umip:1; + uint32_t :1; /* 12 reserved */ + bool vmxe:1; + bool smxe:1; + uint32_t :1; /* 15 reserved */ + bool fsgsbase:1; + bool pcide:1; + bool osxsave:1; + uint32_t :1; /* 19 reserved */ + bool smep:1; + bool smap:1; + bool pke:1; + uint32_t :9; /* 23:31 reserved */ +}; + /* MSR policy object for shared per-domain MSRs */ struct msr_domain_policy { @@ -210,6 +375,214 @@ struct msr_domain_policy bool available; /* This MSR is non-architectural */ bool cpuid_faulting; } plaform_info; + + union { + uint64_t raw[MSR_IA32_VMX_VMCS_ENUM - MSR_IA32_VMX_BASIC + 1]; + + struct { + /* 0x00000480 MSR_IA32_VMX_BASIC */ + union { + uint64_t raw; + struct { + uint32_t vmcs_revision_id:31; + bool mbz:1; /* 31 always zero */ + uint32_t vmcs_region_size:13; + uint32_t :3; /* 45:47 reserved */ + bool addresses_32bit:1; + bool dual_monitor:1; + uint32_t memory_type:4; + bool ins_out_info:1; + bool default1_zero:1; + uint32_t :8; /* 56:63 reserved */ + }; + } basic; + + /* 0x00000481 MSR_IA32_VMX_PINBASED_CTLS */ + union { + uint64_t raw; + struct { + union vmx_pin_based_exec_control_bits allowed_0; + union vmx_pin_based_exec_control_bits allowed_1; + }; + } pinbased_ctls; + + /* 0x00000482 MSR_IA32_VMX_PROCBASED_CTLS */ + union { + uint64_t raw; + struct { + union vmx_cpu_based_exec_control_bits allowed_0; + union vmx_cpu_based_exec_control_bits allowed_1; + }; + } procbased_ctls; + + /* 0x00000483 MSR_IA32_VMX_EXIT_CTLS */ + union { + uint64_t raw; + struct { + union vmx_vmexit_control_bits allowed_0; + union vmx_vmexit_control_bits allowed_1; + }; + } exit_ctls; + + /* 0x00000484 MSR_IA32_VMX_ENTRY_CTLS */ + union { + uint64_t raw; + struct { + union vmx_vmentry_control_bits allowed_0; + union vmx_vmentry_control_bits allowed_1; + }; + } entry_ctls; + + /* 0x00000485 MSR_IA32_VMX_MISC */ + union { + uint64_t raw; + struct { + uint32_t preempt_timer_scale:5; + bool vmexit_stores_lma:1; + bool hlt_activity_state:1; + bool shutdown_activity_state:1; + bool wait_for_sipi_activity_state:1; + uint32_t :5; /* 9:13 reserved */ + bool pt_in_vmx:1; + bool ia32_smbase_support:1; + uint32_t cr3_target:9; + uint32_t max_msr_load_count:3; + bool ia32_smm_monitor_ctl_bit2:1; + bool vmwrite_all:1; + bool inject_ilen0_event:1; + uint32_t :1; /* 31 reserved */ + uint32_t mseg_revision_id; + }; + } misc; + + /* 0x00000486 MSR_IA32_VMX_CR0_FIXED0 */ + union { + uint64_t raw; + struct cr0_bits allowed_0; + } cr0_fixed0; + + /* 0x00000487 MSR_IA32_VMX_CR0_FIXED1 */ + union { + uint64_t raw; + struct cr0_bits allowed_1; + } cr0_fixed1; + + /* 0x00000488 MSR_IA32_VMX_CR4_FIXED0 */ + union { + uint64_t raw; + struct cr4_bits allowed_0; + } cr4_fixed0; + + /* 0x00000489 MSR_IA32_VMX_CR4_FIXED1 */ + union { + uint64_t raw; + struct cr4_bits allowed_1; + } cr4_fixed1; + + /* 0x0000048A MSR_IA32_VMX_VMCS_ENUM */ + union { + uint64_t raw; + struct { + uint32_t :1; /* 0 reserved */ + uint32_t vmcs_encoding_max_idx:9; + uint64_t :54; /* 10:63 reserved */ + }; + } vmcs_enum; + }; + } vmx; + + /* 0x0000048B MSR_IA32_VMX_PROCBASED_CTLS2 */ + union { + uint64_t raw; + struct { + union vmx_secondary_exec_control_bits allowed_0; + union vmx_secondary_exec_control_bits allowed_1; + }; + } vmx_procbased_ctls2; + + /* 0x0000048C MSR_IA32_VMX_EPT_VPID_CAP */ + union { + uint64_t raw; + struct { + bool exec_only_supported:1; + uint32_t :5; /* 1:5 reserved */ + bool walk_length_4_supported:1; + uint32_t :1; /* 7 reserved */ + bool memory_type_uc:1; + uint32_t :5; /* 9:13 reserved */ + bool memory_type_wb:1; + uint32_t :1; /* 15 reserved */ + bool superpage_2mb:1; + bool superpage_1gb:1; + uint32_t :2; /* 18:19 reserved */ + bool invept_instruction:1; + bool ad_bit:1; + bool advanced_ept_violations:1; + uint32_t :2; /* 23:24 reserved */ + bool invept_single_context:1; + bool invept_all_context:1; + uint32_t :5; /* 27:31 reserved */ + bool invvpid_instruction:1; + uint32_t :7; /* 33:39 reserved */ + bool invvpid_individual_addr:1; + bool invvpid_single_context:1; + bool invvpid_all_context:1; + bool invvpid_single_context_retaining_global:1; + uint32_t :20; /* 44:63 reserved */ + }; + } vmx_ept_vpid_cap; + + union { + uint64_t raw[MSR_IA32_VMX_TRUE_ENTRY_CTLS - + MSR_IA32_VMX_TRUE_PINBASED_CTLS + 1]; + + struct { + /* 0x0000048D MSR_IA32_VMX_TRUE_PINBASED_CTLS */ + union { + uint64_t raw; + struct { + union vmx_pin_based_exec_control_bits allowed_0; + union vmx_pin_based_exec_control_bits allowed_1; + }; + } pinbased; + + /* 0x0000048E MSR_IA32_VMX_TRUE_PROCBASED_CTLS */ + union { + uint64_t raw; + struct { + union vmx_cpu_based_exec_control_bits allowed_0; + union vmx_cpu_based_exec_control_bits allowed_1; + }; + } procbased; + + /* 0x0000048F MSR_IA32_VMX_TRUE_EXIT_CTLS */ + union { + uint64_t raw; + struct { + union vmx_vmexit_control_bits allowed_0; + union vmx_vmexit_control_bits allowed_1; + }; + } exit; + + /* 0x00000490 MSR_IA32_VMX_TRUE_ENTRY_CTLS */ + union { + uint64_t raw; + struct { + union vmx_vmentry_control_bits allowed_0; + union vmx_vmentry_control_bits allowed_1; + }; + } entry; + }; + } vmx_true_ctls; + + /* 0x00000491 MSR_IA32_VMX_VMFUNC */ + union { + uint64_t raw; + struct { + bool eptp_switching:1; + uint64_t :63; /* 1:63 reserved */ + }; + } vmx_vmfunc; }; /* MSR policy object for per-vCPU MSRs */