From patchwork Wed Oct 18 08:27:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sergey Dyasli X-Patchwork-Id: 10014109 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 724BD60215 for ; Wed, 18 Oct 2017 08:30:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5FFDD28AF8 for ; Wed, 18 Oct 2017 08:30:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 54EF428AFC; Wed, 18 Oct 2017 08:30:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8EB4628AF8 for ; Wed, 18 Oct 2017 08:30:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4jiH-0002jT-O5; Wed, 18 Oct 2017 08:28:29 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4jiG-0002hp-KE for xen-devel@lists.xen.org; Wed, 18 Oct 2017 08:28:28 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 71/4C-24473-BA017E95; Wed, 18 Oct 2017 08:28:27 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRWlGSWpSXmKPExsXitHRDpO5qgee RBpsvSVgs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBlLtk1jL9gcWnFz0XOWBsYndl2MnBwSAv4S b5umsYPYbAJ6Ehtnv2ICsUUEZCVWd80BinNxMAscYZSYuuoIWJGwgJtEz5wbjCA2i4CqxKUrx 5i7GDk4eAVsJA5tiIGYKS+xq+0iK4jNKWArcf30GjYQWwio5Pebq2BxXgFBiZMzn7CA2MwCmh Kt23+zQ9jyEs1bZzND1KtKvH6xi2UCI98sJC2zkLTMQtKygJF5FaNGcWpRWWqRrpGRXlJRZnp GSW5iZo6uoYGxXm5qcXFiempOYlKxXnJ+7iZGYLDVMzAw7mCcesLvEKMkB5OSKK/ugWeRQnxJ +SmVGYnFGfFFpTmpxYcYZTg4lCR4NfifRwoJFqWmp1akZeYAwx4mLcHBoyTCGwiS5i0uSMwtz kyHSJ1i1OXouHn3D5MQS15+XqqUOG8FSJEASFFGaR7cCFgMXmKUlRLmZWRgYBDiKUgtys0sQZ V/xSjOwagkzOsEMoUnM68EbtMroCOYgI5Y5/QE5IiSRISUVAOjIdttk92ruHi06yS7Sqv4JL7 8ai1nDtDz6snb+KWFkcG0M3iWdLSe+wrmX+rffbnc7k4of2CoFrFP4aZikXlN653Z8us/VP5Y WODnYXrlYeat3DzP771C0d9Eo3+cYeKMPrrzihLv4vUCK8OyTYRt34nmzj07UdCr9+Rc4TKRL YtuJe1fxaLEUpyRaKjFXFScCACUe96fvAIAAA== X-Env-Sender: prvs=457a530fd=sergey.dyasli@citrix.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1508315302!103178682!4 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7541 invoked from network); 18 Oct 2017 08:28:27 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-16.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 18 Oct 2017 08:28:27 -0000 X-IronPort-AV: E=Sophos;i="5.43,395,1503360000"; d="scan'208";a="446828220" From: Sergey Dyasli To: Date: Wed, 18 Oct 2017 09:27:22 +0100 Message-ID: <20171018082722.6279-8-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171018082722.6279-1-sergey.dyasli@citrix.com> References: <20171018082722.6279-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Kevin Tian , Jan Beulich , Jun Nakajima , Sergey Dyasli Subject: [Xen-devel] [PATCH v4 7/7] x86/msr: handle VMX MSRs with guest_rd/wrmsr() X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Now that each domain has a correct view of VMX MSRs in it's per-domain MSR policy, it's possible to handle guest's RD/WRMSR with the new handlers. Do it and remove the old nvmx_msr_read_intercept() and associated bits. There is no functional change to what a guest sees in VMX MSRs. Signed-off-by: Sergey Dyasli --- xen/arch/x86/hvm/vmx/vmx.c | 6 -- xen/arch/x86/hvm/vmx/vvmx.c | 178 ------------------------------------- xen/arch/x86/msr.c | 37 ++++++++ xen/include/asm-x86/hvm/vmx/vvmx.h | 2 - 4 files changed, 37 insertions(+), 186 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index c2148701ee..1a1cb98069 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2906,10 +2906,6 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) if ( nestedhvm_enabled(curr->domain) ) *msr_content |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; break; - case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC: - if ( !nvmx_msr_read_intercept(msr, msr_content) ) - goto gp_fault; - break; case MSR_IA32_MISC_ENABLE: rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content); /* Debug Trace Store is not supported. */ @@ -3133,8 +3129,6 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) break; } case MSR_IA32_FEATURE_CONTROL: - case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: - /* None of these MSRs are writeable. */ goto gp_fault; case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 4d9ffc490c..b0474ad310 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1976,184 +1976,6 @@ int nvmx_handle_invvpid(struct cpu_user_regs *regs) return X86EMUL_OKAY; } -#define __emul_value(enable1, default1) \ - ((enable1 | default1) << 32 | (default1)) - -#define gen_vmx_msr(enable1, default1, host_value) \ - (((__emul_value(enable1, default1) & host_value) & (~0ul << 32)) | \ - ((uint32_t)(__emul_value(enable1, default1) | host_value))) - -/* - * Capability reporting - */ -int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) -{ - struct vcpu *v = current; - struct domain *d = v->domain; - u64 data = 0, host_data = 0; - int r = 1; - - /* VMX capablity MSRs are available only when guest supports VMX. */ - if ( !nestedhvm_enabled(d) || !d->arch.cpuid->basic.vmx ) - return 0; - - /* - * These MSRs are only available when flags in other MSRs are set. - * These prerequisites are listed in the Intel 64 and IA-32 - * Architectures Software Developer’s Manual, Vol 3, Appendix A. - */ - switch ( msr ) - { - case MSR_IA32_VMX_PROCBASED_CTLS2: - if ( !cpu_has_vmx_secondary_exec_control ) - return 0; - break; - - case MSR_IA32_VMX_EPT_VPID_CAP: - if ( !(cpu_has_vmx_ept || cpu_has_vmx_vpid) ) - return 0; - break; - - case MSR_IA32_VMX_TRUE_PINBASED_CTLS: - case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: - case MSR_IA32_VMX_TRUE_EXIT_CTLS: - case MSR_IA32_VMX_TRUE_ENTRY_CTLS: - if ( !(vmx_basic_msr & VMX_BASIC_DEFAULT1_ZERO) ) - return 0; - break; - - case MSR_IA32_VMX_VMFUNC: - if ( !cpu_has_vmx_vmfunc ) - return 0; - break; - } - - rdmsrl(msr, host_data); - - /* - * Remove unsupport features from n1 guest capability MSR - */ - switch (msr) { - case MSR_IA32_VMX_BASIC: - { - const struct vmcs_struct *vmcs = - map_domain_page(_mfn(PFN_DOWN(v->arch.hvm_vmx.vmcs_pa))); - - data = (host_data & (~0ul << 32)) | - (vmcs->vmcs_revision_id & 0x7fffffff); - unmap_domain_page(vmcs); - break; - } - case MSR_IA32_VMX_PINBASED_CTLS: - case MSR_IA32_VMX_TRUE_PINBASED_CTLS: - /* 1-settings */ - data = PIN_BASED_EXT_INTR_MASK | - PIN_BASED_NMI_EXITING | - PIN_BASED_PREEMPT_TIMER; - data = gen_vmx_msr(data, VMX_PINBASED_CTLS_DEFAULT1, host_data); - break; - case MSR_IA32_VMX_PROCBASED_CTLS: - case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: - { - u32 default1_bits = VMX_PROCBASED_CTLS_DEFAULT1; - /* 1-settings */ - data = CPU_BASED_HLT_EXITING | - CPU_BASED_VIRTUAL_INTR_PENDING | - CPU_BASED_CR8_LOAD_EXITING | - CPU_BASED_CR8_STORE_EXITING | - CPU_BASED_INVLPG_EXITING | - CPU_BASED_CR3_LOAD_EXITING | - CPU_BASED_CR3_STORE_EXITING | - CPU_BASED_MONITOR_EXITING | - CPU_BASED_MWAIT_EXITING | - CPU_BASED_MOV_DR_EXITING | - CPU_BASED_ACTIVATE_IO_BITMAP | - CPU_BASED_USE_TSC_OFFSETING | - CPU_BASED_UNCOND_IO_EXITING | - CPU_BASED_RDTSC_EXITING | - CPU_BASED_MONITOR_TRAP_FLAG | - CPU_BASED_VIRTUAL_NMI_PENDING | - CPU_BASED_ACTIVATE_MSR_BITMAP | - CPU_BASED_PAUSE_EXITING | - CPU_BASED_RDPMC_EXITING | - CPU_BASED_TPR_SHADOW | - CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; - - if ( msr == MSR_IA32_VMX_TRUE_PROCBASED_CTLS ) - default1_bits &= ~(CPU_BASED_CR3_LOAD_EXITING | - CPU_BASED_CR3_STORE_EXITING | - CPU_BASED_INVLPG_EXITING); - - data = gen_vmx_msr(data, default1_bits, host_data); - break; - } - case MSR_IA32_VMX_PROCBASED_CTLS2: - /* 1-settings */ - data = SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING | - SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | - SECONDARY_EXEC_ENABLE_VPID | - SECONDARY_EXEC_UNRESTRICTED_GUEST | - SECONDARY_EXEC_ENABLE_EPT; - data = gen_vmx_msr(data, 0, host_data); - break; - case MSR_IA32_VMX_EXIT_CTLS: - case MSR_IA32_VMX_TRUE_EXIT_CTLS: - /* 1-settings */ - data = VM_EXIT_ACK_INTR_ON_EXIT | - VM_EXIT_IA32E_MODE | - VM_EXIT_SAVE_PREEMPT_TIMER | - VM_EXIT_SAVE_GUEST_PAT | - VM_EXIT_LOAD_HOST_PAT | - VM_EXIT_SAVE_GUEST_EFER | - VM_EXIT_LOAD_HOST_EFER | - VM_EXIT_LOAD_PERF_GLOBAL_CTRL; - data = gen_vmx_msr(data, VMX_EXIT_CTLS_DEFAULT1, host_data); - break; - case MSR_IA32_VMX_ENTRY_CTLS: - case MSR_IA32_VMX_TRUE_ENTRY_CTLS: - /* 1-settings */ - data = VM_ENTRY_LOAD_GUEST_PAT | - VM_ENTRY_LOAD_GUEST_EFER | - VM_ENTRY_LOAD_PERF_GLOBAL_CTRL | - VM_ENTRY_IA32E_MODE; - data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data); - break; - - case MSR_IA32_VMX_VMCS_ENUM: - /* The max index of VVMCS encoding is 0x1f. */ - data = 0x1f << 1; - break; - case MSR_IA32_VMX_CR0_FIXED0: - /* PG, PE bits must be 1 in VMX operation */ - data = X86_CR0_PE | X86_CR0_PG; - break; - case MSR_IA32_VMX_CR0_FIXED1: - /* allow 0-settings for all bits */ - data = 0xffffffff; - break; - case MSR_IA32_VMX_CR4_FIXED0: - /* VMXE bit must be 1 in VMX operation */ - data = X86_CR4_VMXE; - break; - case MSR_IA32_VMX_CR4_FIXED1: - data = hvm_cr4_guest_valid_bits(d, false); - break; - case MSR_IA32_VMX_MISC: - /* Do not support CR3-target feature now */ - data = host_data & ~VMX_MISC_CR3_TARGET; - break; - case MSR_IA32_VMX_EPT_VPID_CAP: - data = nept_get_ept_vpid_cap(); - break; - default: - r = 0; - break; - } - - *msr_content = data; - return r; -} - /* This function uses L2_gpa to walk the P2M page table in L1. If the * walk is successful, the translated value is returned in * L1_gpa. The result value tells what to do next. diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9ea7447de3..a1c48b6769 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -360,8 +360,10 @@ int init_vcpu_msr_policy(struct vcpu *v) int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) { + const struct domain *d = v->domain; const struct msr_domain_policy *dp = v->domain->arch.msr; const struct msr_vcpu_policy *vp = v->arch.msr; + const struct cpuid_policy *p = d->arch.cpuid; switch ( msr ) { @@ -379,6 +381,37 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) _MSR_MISC_FEATURES_CPUID_FAULTING; break; + case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMCS_ENUM: + if ( !nestedhvm_enabled(d) || !p->basic.vmx ) + goto gp_fault; + *val = dp->vmx.raw[msr - MSR_IA32_VMX_BASIC]; + break; + + case MSR_IA32_VMX_PROCBASED_CTLS2: + if ( !dp->vmx.procbased_ctls.allowed_1.activate_secondary_controls ) + goto gp_fault; + *val = dp->vmx_procbased_ctls2.raw; + break; + + case MSR_IA32_VMX_EPT_VPID_CAP: + if ( !(dp->vmx_procbased_ctls2.allowed_1.enable_ept || + dp->vmx_procbased_ctls2.allowed_1.enable_vpid) ) + goto gp_fault; + *val = dp->vmx_ept_vpid_cap.raw; + break; + + case MSR_IA32_VMX_TRUE_PINBASED_CTLS ... MSR_IA32_VMX_TRUE_ENTRY_CTLS: + if ( !dp->vmx.basic.default1_zero ) + goto gp_fault; + *val = dp->vmx_true_ctls.raw[msr - MSR_IA32_VMX_TRUE_PINBASED_CTLS]; + break; + + case MSR_IA32_VMX_VMFUNC: + if ( !dp->vmx_procbased_ctls2.allowed_1.enable_vm_functions ) + goto gp_fault; + *val = dp->vmx_vmfunc.raw; + break; + default: return X86EMUL_UNHANDLEABLE; } @@ -423,6 +456,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) break; } + case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: + /* None of these MSRs are writeable. */ + goto gp_fault; + default: return X86EMUL_UNHANDLEABLE; } diff --git a/xen/include/asm-x86/hvm/vmx/vvmx.h b/xen/include/asm-x86/hvm/vmx/vvmx.h index 3285b03bbb..5950672e93 100644 --- a/xen/include/asm-x86/hvm/vmx/vvmx.h +++ b/xen/include/asm-x86/hvm/vmx/vvmx.h @@ -222,8 +222,6 @@ int nvmx_handle_vmresume(struct cpu_user_regs *regs); int nvmx_handle_vmlaunch(struct cpu_user_regs *regs); int nvmx_handle_invept(struct cpu_user_regs *regs); int nvmx_handle_invvpid(struct cpu_user_regs *regs); -int nvmx_msr_read_intercept(unsigned int msr, - u64 *msr_content); void nvmx_update_exec_control(struct vcpu *v, u32 value); void nvmx_update_secondary_exec_control(struct vcpu *v,