From patchwork Wed Oct 18 13:41:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 10014717 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A0EC460215 for ; Wed, 18 Oct 2017 13:44:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9478A28B5D for ; Wed, 18 Oct 2017 13:44:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86B6828B59; Wed, 18 Oct 2017 13:44:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E371228ACB for ; Wed, 18 Oct 2017 13:44:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4obx-0004vV-HW; Wed, 18 Oct 2017 13:42:17 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e4obw-0004vE-KS for xen-devel@lists.xenproject.org; Wed, 18 Oct 2017 13:42:16 +0000 Received: from [85.158.139.211] by server-5.bemta-5.messagelabs.com id D0/46-11148-73A57E95; Wed, 18 Oct 2017 13:42:15 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTdc86nm kQesvDovvWyYzOTB6HP5whSWAMYo1My8pvyKBNaOx+Q1rwR61ihWf/RsYf0p3MXJxCAlsYJT4 1fSIEcJZzihx+890ti5GTg42AV2JHTdfM4PYIgJGEi8eXWYBKWIWmMsosX76MdYuRg4OYQF7i bWHw0FqWARUJdb+v8sKYvMKWEucbl7DBGJLCMhLnHtwmxmknBMoPvVnLEhYSMBK4vWzF6wTGL kXMDKsYtQoTi0qSy3SNbLQSyrKTM8oyU3MzNE1NDDVy00tLk5MT81JTCrWS87P3cQI9G49AwP jDsa+VX6HGCU5mJREeXUPPIsU4kvKT6nMSCzOiC8qzUktPsQow8GhJMFrEfk8UkiwKDU9tSIt MwcYZjBpCQ4eJRHeqAigNG9xQWJucWY6ROoUoy5Hx827f5iEWPLy81KlxHkjQWYIgBRllObBj YCF/CVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrx+IFN4MvNK4Da9AjqCCeiIdU5PQI4oSU RISTUwZqZWbNFd0D7L+KFay2KzGRJ8LM5xX2p3Tcxx1uTb/878uXrNpx3BelE2/2bnT+ZOaPX eIRiTs2ytXXwu+ysept1nJriW1pbpixyOrL+3NmHx35ddZzS9zpedyK6tXjrD+txVj72nY/NP PWI1PawpP9Hd//AFATO5aJWiyu8sc+2dAv/fnbxQiaU4I9FQi7moOBEAY+fSYHQCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-8.tower-206.messagelabs.com!1508334134!107415873!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 64058 invoked from network); 18 Oct 2017 13:42:14 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-8.tower-206.messagelabs.com with SMTP; 18 Oct 2017 13:42:14 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89C7BF; Wed, 18 Oct 2017 06:42:13 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 55EB83F483; Wed, 18 Oct 2017 06:42:12 -0700 (PDT) From: Andre Przywara To: Bhupinder Thakur Date: Wed, 18 Oct 2017 14:41:58 +0100 Message-Id: <20171018134158.32633-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <8dc5e662-4cbd-908d-4f3e-af372d6d0917@arm.com> References: <8dc5e662-4cbd-908d-4f3e-af372d6d0917@arm.com> Cc: xen-devel@lists.xenproject.org, Julien Grall , Stefano Stabellini , Dave Martin Subject: [Xen-devel] [PATCH RFC] ARM: vPL011: use receive timeout interrupt X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of asserting the receive interrupt (RXI) on the first character in the FIFO, lets (ab)use the receive timeout interrupt (RTI) for that purpose. That seems to be closer to the spec and what hardware does. Improve the readability of vpl011_data_avail() on the way. Signed-off-by: Andre Przywara --- Hi, this one is the approach I mentioned in the email earlier today. It goes on top of Bhupinders v12 27/27, but should eventually be merged into this one once we agreed on the subject. I just carved it out here for clarity to make it clearer what has been changed. Would be good if someone could test it. Cheers, Andre. xen/arch/arm/vpl011.c | 61 ++++++++++++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index adf1711571..ae18bddd81 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -105,9 +105,13 @@ static uint8_t vpl011_read_data(struct domain *d) if ( fifo_level == 0 ) { vpl011->uartfr |= RXFE; - vpl011->uartris &= ~RXI; - vpl011_update_interrupt_status(d); + vpl011->uartris &= ~RTI; } + + if ( fifo_level < sizeof(intf->in) - SBSA_UART_FIFO_SIZE / 2 ) + vpl011->uartris &= ~RXI; + + vpl011_update_interrupt_status(d); } else gprintk(XENLOG_ERR, "vpl011: Unexpected IN ring buffer empty\n"); @@ -129,7 +133,7 @@ static void vpl011_update_tx_fifo_status(struct vpl011 *vpl011, unsigned int fifo_level) { struct xencons_interface *intf = vpl011->ring_buf; - unsigned int fifo_threshold; + unsigned int fifo_threshold = sizeof(intf->out) - SBSA_UART_FIFO_SIZE/2; BUILD_BUG_ON(sizeof (intf->out) < SBSA_UART_FIFO_SIZE); @@ -137,8 +141,6 @@ static void vpl011_update_tx_fifo_status(struct vpl011 *vpl011, * Set the TXI bit only when there is space for fifo_size/2 bytes which * is the trigger level for asserting/de-assterting the TX interrupt. */ - fifo_threshold = sizeof(intf->out) - SBSA_UART_FIFO_SIZE/2; - if ( fifo_level <= fifo_threshold ) vpl011->uartris |= TXI; else @@ -390,35 +392,30 @@ static void vpl011_data_avail(struct domain *d) out_cons, sizeof(intf->out)); - /* Update the uart rx state if the buffer is not empty. */ - if ( in_fifo_level != 0 ) - { + /**** Update the UART RX state ****/ + + /* Clear the FIFO_EMPTY bit if the FIFO holds at least one character. */ + if ( in_fifo_level > 0 ) vpl011->uartfr &= ~RXFE; - if ( in_fifo_level == sizeof(intf->in) ) - vpl011->uartfr |= RXFF; + /* Set the FIFO_FULL bit if the ring buffer is full. */ + if ( in_fifo_level == sizeof(intf->in) ) + vpl011->uartfr |= RXFF; - /* - * Currently, the RXI bit is getting set even if there is a single - * byte of data in the rx fifo. Ideally, the RXI bit should be set - * only if the rx fifo level reaches the threshold. - * - * However, since currently RX timeout interrupt is not - * implemented as there is not enough clarity in the SBSA spec, - * the guest may keep waiting for an interrupt to read more - * data. To ensure that guest reads all the data without - * any delay, the RXI interrupt is raised if there is RX data - * available without checking whether fifo level has reached - * the threshold. - * - * TBD: Once there is more clarity in the SBSA spec on whether RX - * timeout interrupt needs to be implemented, the RXI interrupt - * will be raised only when rx fifo level reaches the threshold. - */ + /* The FIFO trigger level is fixed to half of the FIFO. */ + if ( in_fifo_level >= sizeof(intf->in) - SBSA_UART_FIFO_SIZE / 2 ) vpl011->uartris |= RXI; - } - /* Update the uart tx state if the buffer is not full. */ + /* + * If the input queue is not empty, we assert the receive timeout interrupt. + * As we don't emulate any timing here, we ignore the actual timeout + * of 32 bit periods. + */ + if ( in_fifo_level > 0 ) + vpl011->uartris |= RTI; + + /**** Update the UART TX state ****/ + if ( out_fifo_level != sizeof(intf->out) ) { vpl011->uartfr &= ~TXFF; @@ -431,13 +428,13 @@ static void vpl011_data_avail(struct domain *d) vpl011->uartfr &= ~BUSY; vpl011_update_tx_fifo_status(vpl011, out_fifo_level); - - if ( out_fifo_level == 0 ) - vpl011->uartfr |= TXFE; } vpl011_update_interrupt_status(d); + if ( out_fifo_level == 0 ) + vpl011->uartfr |= TXFE; + VPL011_UNLOCK(d, flags); }