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Thu, 19 Oct 2017 10:09:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id o74sm9281420qkl.58.2017.10.19.10.09.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Oct 2017 10:09:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 19 Oct 2017 18:09:05 +0100 Message-Id: <20171019170905.14314-1-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 Cc: sstabellini@kernel.org, Julien Grall , andre.przywara@linaro.org Subject: [Xen-devel] [PATCH for-4.10] xen/arm: gic-v3: Make sure ICC_SRE_EL1 is restored before ICH_VMCR_EL2 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Per 8.4.8 in ARM IHI 0069D, ICH_VMCR_EL2.VFIQEn is RES1 when ICC_SRE_EL1.SRE is 1. This causes a Group 0 interrupt (as generated in GICv2 mode) to be delivered as a FIQ to the guest, with potentially consequence. So we must make sure that ICC_SRE_EL1 has been actually programmed before at ICH_VMCR_EL2. This was discovered when booting EFI in a GICv2 guest on a GICv3 hardware. Signed-off-by: Julien Grall Signed-off-by: Stefano Stabellini --- This patch should be backported up to Xen 4.7. --- xen/arch/arm/gic-v3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 74d00e0c54..b8aff77a6c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -392,7 +392,16 @@ static void gicv3_restore_state(const struct vcpu *v) val |= GICC_SRE_EL2_ENEL1; WRITE_SYSREG32(val, ICC_SRE_EL2); + /* + * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a Group0 + * interrupt (as generated in GICv2 mode) to be delivered as a FIQ + * to the guest, with potentially consequence. So we must make sure + * that ICC_SRE_EL1 has been actually programmed with the value we + * want before starting to mess with the rest of the GIC, and + * VMCR_EL1 in particular. + */ WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); + isb(); WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); restore_aprn_regs(&v->arch.gic); gicv3_restore_lrs(v);