From patchwork Thu Jul 4 14:42:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anthony PERARD X-Patchwork-Id: 11031565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 447C4112C for ; Thu, 4 Jul 2019 14:44:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33C1D286F3 for ; Thu, 4 Jul 2019 14:44:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 281C728AA1; Thu, 4 Jul 2019 14:44:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A276828AA2 for ; Thu, 4 Jul 2019 14:44:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hj2wg-0003FX-Rf; Thu, 04 Jul 2019 14:42:46 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hj2wf-0003EK-A7 for xen-devel@lists.xenproject.org; Thu, 04 Jul 2019 14:42:45 +0000 X-Inumbo-ID: faf3ec72-9e69-11e9-bcba-bb981a0739d6 Received: from esa2.hc3370-68.iphmx.com (unknown [216.71.145.153]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id faf3ec72-9e69-11e9-bcba-bb981a0739d6; Thu, 04 Jul 2019 14:42:43 +0000 (UTC) Authentication-Results: esa2.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=anthony.perard@citrix.com; spf=Pass smtp.mailfrom=anthony.perard@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of anthony.perard@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="anthony.perard@citrix.com"; x-sender="anthony.perard@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa2.hc3370-68.iphmx.com: domain of anthony.perard@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="anthony.perard@citrix.com"; x-sender="anthony.perard@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ~all" Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="anthony.perard@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: e3aeL0hkoFld3nP/bMLrhKmsxsWofztx6A8gStIF4QYlq0X/rO9spehq526rkOyDedAEO9zj9e e9DcXNLELM/4MArx/ldyJC0MDm6LScxR2OHJrqRP9l4sNNJxpLor51FOBw6a9TMcvYTWdMkW9R FhwZnLkJyyJt9f90vtbbR9Fi+dIyClG8zu7l0LFxKiS0wFVtV3Lm5IQlRkeAIqz1hGGUjmKIqr JxAODj3aAq5JMDTGfkDwLWqhjJfVNG1FnOkgge6LTpM4mPOnLvp95PGq+dV1i5zUXiVkHMVXLp foU= X-SBRS: 2.7 X-MesageID: 2588787 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.63,451,1557201600"; d="scan'208";a="2588787" From: Anthony PERARD To: Date: Thu, 4 Jul 2019 15:42:04 +0100 Message-ID: <20190704144233.27968-7-anthony.perard@citrix.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190704144233.27968-1-anthony.perard@citrix.com> References: <20190704144233.27968-1-anthony.perard@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3 06/35] OvmfPkg/XenResetVector: Add new entry point for Xen PVH X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel , Jordan Justen , Julien Grall , Andrew Cooper , Anthony PERARD , xen-devel@lists.xenproject.org, Laszlo Ersek , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add a new entry point for Xen PVH that enter directly in 32bits. Information on the expected state of the machine when this entry point is used can be found at: https://xenbits.xenproject.org/docs/unstable/misc/pvh.html Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689 Signed-off-by: Anthony PERARD Acked-by: Laszlo Ersek --- Notes: v3: - rebased, SPDX - remove `cli' as via PVH the interrupts are guaranteed to be off - rewrite some comments .../XenResetVector/Ia16/ResetVectorVtf0.asm | 81 +++++++++++++++++++ OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm | 49 +++++++++++ OvmfPkg/XenResetVector/XenResetVector.nasmb | 1 + 3 files changed, 131 insertions(+) create mode 100644 OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm create mode 100644 OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm diff --git a/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm new file mode 100644 index 0000000000..958195bc5e --- /dev/null +++ b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,81 @@ +;------------------------------------------------------------------------------ +; @file +; First code executed by processor after resetting. +; +; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 16 + +ALIGN 16 + +; +; Pad the image size to 4k when page tables are in VTF0 +; +; If the VTF0 image has page tables built in, then we need to make +; sure the end of VTF0 is 4k above where the page tables end. +; +; This is required so the page tables will be 4k aligned when VTF0 is +; located just below 0x100000000 (4GB) in the firmware device. +; +%ifdef ALIGN_TOP_TO_4K_FOR_PAGING + TIMES (0x1000 - ($ - EndOfPageTables) - (fourGigabytes - xenPVHEntryPoint)) DB 0 +%endif + +BITS 32 +xenPVHEntryPoint: +; +; Entry point to use when running as a Xen PVH guest. (0xffffffd0) +; +; Description of the expected state of the machine when this entry point is +; used can be found at: +; https://xenbits.xenproject.org/docs/unstable/misc/pvh.html +; + jmp xenPVHMain + +BITS 16 +ALIGN 16 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + nop + nop + jmp EarlyBspInitReal16 + +ALIGN 16 + +fourGigabytes: + diff --git a/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm new file mode 100644 index 0000000000..2a17fed52f --- /dev/null +++ b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm @@ -0,0 +1,49 @@ +;------------------------------------------------------------------------------ +; @file +; An entry point use by Xen when a guest is started in PVH mode. +; +; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 32 + +xenPVHMain: + ; + ; 'BP' to indicate boot-strap processor + ; + mov di, 'BP' + + ; + ; ESP will be used as initial value of the EAX register + ; in Main.asm + ; + xor esp, esp + + mov ebx, ADDR_OF(gdtr) + lgdt [ebx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:ADDR_OF(.jmpToNewCodeSeg) +.jmpToNewCodeSeg: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; Jump to the main routine of the pre-SEC code + ; skiping the 16-bit part of the routine and + ; into the 32-bit flat mode part + ; + OneTimeCallRet TransitionFromReal16To32BitFlat diff --git a/OvmfPkg/XenResetVector/XenResetVector.nasmb b/OvmfPkg/XenResetVector/XenResetVector.nasmb index 89a4b08bc3..0dbc4f2c1d 100644 --- a/OvmfPkg/XenResetVector/XenResetVector.nasmb +++ b/OvmfPkg/XenResetVector/XenResetVector.nasmb @@ -63,6 +63,7 @@ %include "Ia16/Init16.asm" %include "Main.asm" +%include "Ia32/XenPVHMain.asm" %include "Ia16/ResetVectorVtf0.asm"