From patchwork Mon Aug 12 17:29:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 11090315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D61C1399 for ; Mon, 12 Aug 2019 17:32:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E214283A5 for ; Mon, 12 Aug 2019 17:32:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 622E4284DB; Mon, 12 Aug 2019 17:32:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 10F47283A5 for ; Mon, 12 Aug 2019 17:32:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9S-0006gy-OS; Mon, 12 Aug 2019 17:30:34 +0000 Received: from [172.99.69.81] (helo=us1-rack-iad1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9R-0006ge-KT for xen-devel@lists.xenproject.org; Mon, 12 Aug 2019 17:30:33 +0000 X-Inumbo-ID: e29140f4-bd26-11e9-8483-13847f7cc42a Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id e29140f4-bd26-11e9-8483-13847f7cc42a; Mon, 12 Aug 2019 17:30:31 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC39E19BF; Mon, 12 Aug 2019 10:30:31 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 16AA23F706; Mon, 12 Aug 2019 10:30:30 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:29:56 +0100 Message-Id: <20190812173019.11956-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 05/28] xen/arm64: head: Setup TTBR_EL2 in enable_mmu() and add missing isb X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP At the moment, TTBR_EL2 is setup in create_page_tables(). This is fine as it is called by every CPUs. However, such assumption may not hold in the future. To make change easier, the TTBR_EL2 is not setup in enable_mmu(). Take the opportunity to add the missing isb() to ensure the TTBR_EL2 is seen before the MMU is turned on. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's acked-by Changes in v2: - Patch added --- xen/arch/arm/arm64/head.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 925fb93e58..9b703e79ce 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -507,9 +507,7 @@ create_page_tables: cmp x19, #XEN_VIRT_START cset x25, eq /* x25 := identity map in place, or not */ - /* Write Xen's PT's paddr into TTBR0_EL2 */ load_paddr x4, boot_pgtable - msr TTBR0_EL2, x4 /* Setup boot_pgtable: */ load_paddr x1, boot_first @@ -637,6 +635,11 @@ enable_mmu: tlbi alle2 /* Flush hypervisor TLBs */ dsb nsh + /* Write Xen's PT's paddr into TTBR0_EL2 */ + load_paddr x0, boot_pgtable + msr TTBR0_EL2, x0 + isb + mrs x0, SCTLR_EL2 orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MMU */ orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */