From patchwork Fri Oct 18 13:47:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11198487 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D5631599 for ; Fri, 18 Oct 2019 13:51:56 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 626EC222BD for ; Fri, 18 Oct 2019 13:51:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 626EC222BD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iLSeV-0006C7-De; Fri, 18 Oct 2019 13:50:47 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iLSeU-0006Bj-Px for xen-devel@lists.xenproject.org; Fri, 18 Oct 2019 13:50:46 +0000 X-Inumbo-ID: 48a94902-f1ae-11e9-a531-bc764e2007e4 Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 48a94902-f1ae-11e9-a531-bc764e2007e4; Fri, 18 Oct 2019 13:50:46 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 740D9302C076; Fri, 18 Oct 2019 13:50:45 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.74]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4682F60BF1; Fri, 18 Oct 2019 13:50:38 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Fri, 18 Oct 2019 15:47:49 +0200 Message-Id: <20191018134754.16362-16-philmd@redhat.com> In-Reply-To: <20191018134754.16362-1-philmd@redhat.com> References: <20191018134754.16362-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Fri, 18 Oct 2019 13:50:45 +0000 (UTC) Subject: [Xen-devel] [PATCH v2 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Marcel Apfelbaum , "Michael S. Tsirkin" , Paul Durrant , Paolo Bonzini , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Markovic , Igor Mammedov , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Eduardo Habkost Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/xen/xen-hvm.c | 5 +++-- hw/mips/gt64xxx_pci.c | 4 ++-- hw/pci-host/piix.c | 9 ++++----- include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 6b5e5bb7f5..4ce2fb9c89 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/hw.h" #include "hw/i386/apic-msidef.h" @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len) v = 0; } v &= 0xf; - if (((address + i) >= 0x60) && ((address + i) <= 0x63)) { - xen_set_pci_link_route(xen_domid, address + i - 0x60, v); + if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) { + xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v); } } } diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c277398c0d..5cab9c1ee1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[0x60 + irq_num]; + pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[0x60 + i]) { + if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |= pci_irq_levels[i]; } } diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 6548d9a4b5..390fb9ceba 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -61,7 +61,6 @@ typedef struct I440FXState { #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 typedef struct PIIX3State { PCIDevice dev; @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) int pic_irq; uint64_t mask; - pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= PIIX_NUM_PIC_IRQS) { return; } @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) { int pic_irq; - pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= PIIX_NUM_PIC_IRQS) { return; } @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; - int irq = piix3->dev.config[PIIX_PIRQC + pin]; + int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; if (irq < PIIX_NUM_PIC_IRQS) { @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { pci_default_write_config(dev, address, val, len); - if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { + if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); int pic_irq; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index e49d4a6bbe..094508b928 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + /* * Reset Control Register: PCI-accessible ISA-Compatible Register at address * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).