From patchwork Sat Oct 26 18:01:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E06901920 for ; Sat, 26 Oct 2019 18:04:01 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA98720663 for ; Sat, 26 Oct 2019 18:04:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="J1qBrkZy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA98720663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOT-00057d-57; Sat, 26 Oct 2019 18:02:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOR-00057U-SG for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:02:27 +0000 X-Inumbo-ID: c4a96acf-f81a-11e9-94d7-12813bfff9fa Received: from us-smtp-1.mimecast.com (unknown [205.139.110.120]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id c4a96acf-f81a-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:02:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572112946; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=leKb+mxeE3Ab87XsOqKSMcG+BfzCOIRLFQX4loQ4eOE=; b=J1qBrkZymO4kI+AsqO4NLvn9Gqnu4QSf9aHAR2Tl34uvje4/SrtSPq1QlQIgMZMYk/suWt kA64f92Y6JVGLkzEXw+HdkIUw4FamtSFQzQPeVcO7Hz0uBJFOI45eEsjx1PCAQxDA80CTF uH+4ERLMeeRGHivvh2ZphyIQJRBM3OI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-358-sUwBDL4wNaSRj2Jzaozt5w-1; Sat, 26 Oct 2019 14:02:21 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 07D2E800D41; Sat, 26 Oct 2019 18:02:20 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 03ED460C57; Sat, 26 Oct 2019 18:02:09 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:25 +0200 Message-Id: <20191026180143.7369-3-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: sUwBDL4wNaSRj2Jzaozt5w-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 02/20] piix4: Add the Reset Control Register X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daudé --- v3: Use RCR_IOPORT (Li Qiang) --- hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 890d999abf..7a1361a9dd 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +29,17 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + + s->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s = opaque; + + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops = { + .read = piix4_rcr_read, + .write = piix4_rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIX4State *s = PIIX4_PCI_DEVICE(dev); - if (!isa_bus_new(DEVICE(d), pci_address_space(dev), + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp)) { return; } - piix4_dev = &d->dev; + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + RCR_IOPORT, &s->rcr_mem, 1); + + piix4_dev = dev; } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)