From patchwork Mon Nov 25 17:22:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 11260737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8DDC414DB for ; Mon, 25 Nov 2019 17:23:21 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6920920748 for ; Mon, 25 Nov 2019 17:23:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="ZJwzFOOd" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6920920748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iZI4L-0002O6-V5; Mon, 25 Nov 2019 17:22:37 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iZI4K-0002Nv-Fg for xen-devel@lists.xenproject.org; Mon, 25 Nov 2019 17:22:36 +0000 X-Inumbo-ID: 29dcc89d-0fa8-11ea-a393-12813bfff9fa Received: from esa3.hc3370-68.iphmx.com (unknown [216.71.145.155]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 29dcc89d-0fa8-11ea-a393-12813bfff9fa; Mon, 25 Nov 2019 17:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1574702552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yDVp1LL0C3gqIApehOZdbVQocO/+1vjgC5EWplLyS+g=; b=ZJwzFOOdgCP/TOp2L6RmUfkULNI5IPJqmB/h+MD6X3NS62FbpbwJOflF TPe9jL8TPiz1ToohkDo16D0Y6js9Xgl3G6CATMYgzU5f1WOo4X/lrOj7s i5ILBXsJpGNcYwccb+o9E/rixpSc1Q9/FxgyLFoMoa3/aJjvBd5aB/gnB A=; Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=roger.pau@citrix.com; spf=Pass smtp.mailfrom=roger.pau@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa3.hc3370-68.iphmx.com: no sender authenticity information available from domain of roger.pau@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa3.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa3.hc3370-68.iphmx.com: domain of roger.pau@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa3.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa3.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa3.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: iPksKnYeTMhYWE/QZoznU8HotAXdvRMmeE3koLD2pULWUZGrtZQrLJtQK2HzB0al299lrqNFnL WsVBEr6linaRf9lNboSwI+w4D+xz2OUbN7/bLft0jQ5iZFkdLJEwHp5+TBVzf9BGeGBAJ0TC4o NniGPtufpkyZIrNv+AxCivhZaFybHPXh/QCh48RbVAHS50Iad7r8d0KWTLfFwKEtA+mcDPgcij sVfBG8lp1HIjlJvnpjFrvFeE98Goqhv6EMGXxCFJRkz8x/7jwSY0qCMysswkzeHSQcNpux4Y9l x04= X-SBRS: 2.7 X-MesageID: 8801970 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,242,1571716800"; d="scan'208";a="8801970" From: Roger Pau Monne To: Date: Mon, 25 Nov 2019 18:22:12 +0100 Message-ID: <20191125172213.1904-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191125172213.1904-1-roger.pau@citrix.com> References: <20191125172213.1904-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] x86/tlbflush: do not toggle the PGE CR4 bit unless necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When PCID is not available Xen does a full tlbflush by toggling the PGE bit in CR4. This is not necessary if PGE is not enabled, since a flush can be performed by writing to CR3 in that case. Change the code in do_tlb_flush to only toggle the PGE bit in CR4 if it's already enabled, otherwise do the tlb flush by writing to CR3. This is relevant when running virtualized, since hypervisors don't usually trap accesses to CR3 when using hardware assisted paging, but do trap accesses to CR4 specially on AMD hardware, which makes such accesses much more expensive. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich --- xen/arch/x86/flushtlb.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index c1ae0d9467..540209c856 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -84,6 +84,7 @@ static void post_flush(u32 t) static void do_tlb_flush(void) { unsigned long flags; + unsigned long cr4; u32 t; /* This non-reentrant function is sometimes called in interrupt context. */ @@ -93,13 +94,13 @@ static void do_tlb_flush(void) if ( use_invpcid ) invpcid_flush_all(); - else + else if ( (cr4 = read_cr4()) & X86_CR4_PGE ) { - unsigned long cr4 = read_cr4(); - - write_cr4(cr4 ^ X86_CR4_PGE); + write_cr4(cr4 & ~X86_CR4_PGE); write_cr4(cr4); } + else + write_cr3(read_cr3()); post_flush(t);