| Message ID | 20200123180615.69370-2-roger.pau@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/apic: improvements to disconnect_bsp_APIC | expand |
On 23.01.2020 19:06, Roger Pau Monne wrote: > The Intel SDM states: > > "When an illegal vector value (0 to 15) is written to a LVT entry and > the delivery mode is Fixed (bits 8-11 equal 0), the APIC may signal an > illegal vector error, without regard to whether the mask bit is set or > whether an interrupt is actually seen on the input." > > And that's exactly what's currently done in disconnect_bsp_APIC when > virt_wire_setup is true and LVT LINT0 is being masked. By writing only > APIC_LVT_MASKED Xen is actually setting the vector to 0 and the > delivery mode to Fixed (0), and hence it triggers an APIC error even > when the LVT entry is masked. > > This would usually manifest when Xen is being shut down, as that's > where disconnect_bsp_APIC is called: > > (XEN) APIC error on CPU0: 40(00) > > Fix this by calling clear_local_APIC prior to setting the LVT LINT > registers which already clear LVT LINT0, and hence the troublesome > write can be avoided as the register is already cleared. > > Reported-by: Andrew Cooper <andrew.cooper3@citrix.com> > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index a6a7754d77..508b1586f2 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -262,6 +262,8 @@ void disconnect_bsp_APIC(int virt_wire_setup) /* Go back to Virtual Wire compatibility mode */ unsigned long value; + clear_local_APIC(); + /* For the spurious interrupt use vector F, and enable it */ value = apic_read(APIC_SPIV); value &= ~APIC_VECTOR_MASK; @@ -279,10 +281,6 @@ void disconnect_bsp_APIC(int virt_wire_setup) value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); apic_write(APIC_LVT0, value); } - else { - /* Disable LVT0 */ - apic_write(APIC_LVT0, APIC_LVT_MASKED); - } /* For LVT1 make it edge triggered, active high, nmi and enabled */ value = apic_read(APIC_LVT1);
The Intel SDM states: "When an illegal vector value (0 to 15) is written to a LVT entry and the delivery mode is Fixed (bits 8-11 equal 0), the APIC may signal an illegal vector error, without regard to whether the mask bit is set or whether an interrupt is actually seen on the input." And that's exactly what's currently done in disconnect_bsp_APIC when virt_wire_setup is true and LVT LINT0 is being masked. By writing only APIC_LVT_MASKED Xen is actually setting the vector to 0 and the delivery mode to Fixed (0), and hence it triggers an APIC error even when the LVT entry is masked. This would usually manifest when Xen is being shut down, as that's where disconnect_bsp_APIC is called: (XEN) APIC error on CPU0: 40(00) Fix this by calling clear_local_APIC prior to setting the LVT LINT registers which already clear LVT LINT0, and hence the troublesome write can be avoided as the register is already cleared. Reported-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- Changes since v1: - Use clear_local_APIC in order to clear LINT0. --- xen/arch/x86/apic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)