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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id b67sm4594690wmc.38.2020.02.20.05.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2020 05:06:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Peter Maydell , qemu-devel@nongnu.org Date: Thu, 20 Feb 2020 14:05:38 +0100 Message-Id: <20200220130548.29974-11-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200220130548.29974-1-philmd@redhat.com> References: <20200220130548.29974-1-philmd@redhat.com> MIME-Version: 1.0 X-MC-Unique: 2nsEbd49MZ2DVas3SsuWZg-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Subject: [Xen-devel] [PATCH v3 10/20] Remove unnecessary cast when using the cpu_[physical]_memory API X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Dmitry Fleytman , kvm@vger.kernel.org, "Michael S. Tsirkin" , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Stefano Stabellini , Matthew Rosato , qemu-block@nongnu.org, David Hildenbrand , Halil Pasic , Christian Borntraeger , =?utf-8?q?Herv=C3=A9_Poussi?= =?utf-8?q?neau?= , Marcel Apfelbaum , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Laurent Vivier , Thomas Huth , Eduardo Habkost , Stefan Weil , Alistair Francis , Richard Henderson , Paul Durrant , Eric Auger , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , John Snow , David Gibson , Igor Mitsyanko , Cornelia Huck , Michael Walle , qemu-ppc@nongnu.org, Paolo Bonzini Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const. Suggested-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé --- scripts/coccinelle/exec_rw_const.cocci | 10 ++++++++++ hw/display/omap_lcdc.c | 10 +++++----- hw/dma/etraxfs_dma.c | 25 ++++++++++--------------- hw/scsi/vmw_pvscsi.c | 8 +++----- target/i386/hax-all.c | 6 +++--- 5 files changed, 31 insertions(+), 28 deletions(-) diff --git a/scripts/coccinelle/exec_rw_const.cocci b/scripts/coccinelle/exec_rw_const.cocci index 5ed956a834..70cf52d58e 100644 --- a/scripts/coccinelle/exec_rw_const.cocci +++ b/scripts/coccinelle/exec_rw_const.cocci @@ -34,6 +34,16 @@ type T; + address_space_write_rom(E1, E2, E3, E4, E5) | +- cpu_physical_memory_rw(E1, (T *)E2, E3, E4) ++ cpu_physical_memory_rw(E1, E2, E3, E4) +| +- cpu_physical_memory_read(E1, (T *)E2, E3) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_write(E1, (T *)E2, E3) ++ cpu_physical_memory_write(E1, E2, E3) +| + - dma_memory_read(E1, E2, (T *)E3, E4) + dma_memory_read(E1, E2, E3, E4) | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index 6ad13f2e9e..fa4a381db6 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -91,9 +91,9 @@ static void omap_update_display(void *opaque) frame_offset = 0; if (omap_lcd->plm != 2) { - cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[ - omap_lcd->dma->current_frame], - (void *)omap_lcd->palette, 0x200); + cpu_physical_memory_read( + omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], + omap_lcd->palette, 0x200); switch (omap_lcd->palette[0] >> 12 & 7) { case 3 ... 7: frame_offset += 0x200; @@ -244,8 +244,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) { if (s->plm != 2 && !s->palette_done) { cpu_physical_memory_read( - s->dma->phys_framebuffer[s->dma->current_frame], - (void *)s->palette, 0x200); + s->dma->phys_framebuffer[s->dma->current_frame], + s->palette, 0x200); s->palette_done = 1; omap_lcd_interrupts(s); } diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 47e1c6df12..c4334e87bf 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -225,9 +225,8 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_g, - sizeof ctrl->channels[c].current_g); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_g, + sizeof(ctrl->channels[c].current_g)); } static void dump_c(int ch, struct dma_descr_context *c) @@ -257,9 +256,8 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); D(dump_c(c, &ctrl->channels[c].current_c)); /* I guess this should update the current pos. */ @@ -275,9 +273,8 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) /* Load and decode. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); D(dump_d(c, &ctrl->channels[c].current_d)); ctrl->channels[c].regs[RW_DATA] = addr; @@ -290,9 +287,8 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); } static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) @@ -301,9 +297,8 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); } static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index e4ee2e6643..c91352cf46 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -404,8 +404,7 @@ pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); trace_pvscsi_cmp_ring_put(cmp_descr_pa); - cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, - sizeof(*cmp_desc)); + cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); } static void @@ -415,8 +414,7 @@ pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); trace_pvscsi_msg_ring_put(msg_descr_pa); - cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, - sizeof(*msg_desc)); + cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); } static void @@ -491,7 +489,7 @@ pvscsi_get_next_sg_elem(PVSCSISGState *sg) { struct PVSCSISGElement elem; - cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); + cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { /* * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index a8b6e5aeb8..a9cc51e6ce 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -367,7 +367,7 @@ static int hax_accel_init(MachineState *ms) static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) { if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &hft->value, hft->size, + cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, hft->direction); } else { /* @@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) * hft->direction == 2: gpa ==> gpa2 */ uint64_t value; - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &value, hft->size, 0); - cpu_physical_memory_rw(hft->gpa2, (uint8_t *) &value, hft->size, 1); + cpu_physical_memory_rw(hft->gpa, &value, hft->size, 0); + cpu_physical_memory_rw(hft->gpa2, &value, hft->size, 1); } return 0;