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Mon, 24 Aug 2020 03:28:39 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v2 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Date: Mon, 24 Aug 2020 03:28:24 +0000 Message-ID: <20200824032825.18368-2-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200824032825.18368-1-wei.chen@arm.com> References: <20200824032825.18368-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1ff2c318-66ed-48d5-c2b6-08d847ddd1ec X-MS-TrafficTypeDiagnostic: AM6PR08MB4582:|DBAPR08MB5558: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:7691;OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: MBZi2oeAXQNPAFJxKsa0qYoF5IIfuQ85zqSu80Bsy2XaQApWnVlR8x44gbyRZGqFbTBP45VQwMZ1jSmTDxpzFXuVIR/tSvNv5b62KCKK6MFhImQpOu05Ztc1IRrjJnbFZYuTt/WvXksEm9cYEyqWucEZe3YZPlA+IpinUrnd+GZQe0bNDnbQZdfZFE4WBFdKE8xpt9IfxkigOcKXMZhlagBHq3iqAiEk6TUlESY4VJrqeuZhPbNzP0I0Gd4LYoYz+G2POpDL7cS6TZKMWA3lRt9GkHai3aMImMZYigRtGo80hPsFhWZv8OSZ8WNBQ0RtMHUQ+S+FLT4sFXS6k2aBe138EwQAGW1HyKwqcszDSTXdegktJOKq/amJiy25iuQCkzHkjfEpGFU9FrRqmFFxQA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(39850400004)(396003)(346002)(376002)(46966005)(8936002)(186003)(2906002)(44832011)(4326008)(5660300002)(1076003)(70206006)(70586007)(26005)(36756003)(6666004)(336012)(426003)(8676002)(478600001)(83380400001)(36906005)(82310400002)(81166007)(316002)(54906003)(47076004)(82740400003)(110136005)(2616005)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2020 03:28:50.7654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ff2c318-66ed-48d5-c2b6-08d847ddd1ec X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT014.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5558 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports FP/SIMD or not. But currently, these two MACROs only consider value 0 of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs that support FP/SIMD and half-precision floating-point arithmetic, the ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64). For these CPUs, xen will treat them as no FP/SIMD supporti, the vfp_save/restore_state will not take effect. From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support basic Advanced SIMD/FP and half-precision floating-point arithmetic. In this case, on N1/A76/A75 platforms, Xen will always miss the floating pointer registers save/restore. If different vCPUs are running on the same pCPU, the floating pointer registers will be corrupted randomly. This patch fixes Xen on these new cores. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Reviewed-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 674beb0353..10878ead8a 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -13,8 +13,8 @@ #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) +#define cpu_has_fp (boot_cpu_feature64(fp) < 8) +#define cpu_has_simd (boot_cpu_feature64(simd) < 8) #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) #endif