@@ -519,6 +519,14 @@ static inline bool apic_id_is_primary_th
static inline void apic_smt_update(void) { }
#endif
+struct msi_msg;
+
+#ifdef CONFIG_PCI_MSI
+void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);
+#else
+# define x86_vector_msi_compose_msg NULL
+#endif
+
extern void ioapic_zap_locks(void);
#endif /* _ASM_X86_APIC_H */
@@ -45,7 +45,7 @@ static void __irq_msi_compose_msg(struct
MSI_DATA_VECTOR(cfg->vector);
}
-static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
__irq_msi_compose_msg(irqd_cfg(data), msg);
}
@@ -177,7 +177,6 @@ static struct irq_chip pci_msi_controlle
.irq_mask = pci_msi_mask_irq,
.irq_ack = irq_chip_ack_parent,
.irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_compose_msi_msg = irq_msi_compose_msg,
.irq_set_affinity = msi_set_affinity,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
@@ -321,7 +320,6 @@ static struct irq_chip dmar_msi_controll
.irq_ack = irq_chip_ack_parent,
.irq_set_affinity = msi_domain_set_affinity,
.irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_compose_msi_msg = irq_msi_compose_msg,
.irq_write_msi_msg = dmar_msi_write_msg,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
@@ -419,7 +417,6 @@ static struct irq_chip hpet_msi_controll
.irq_ack = irq_chip_ack_parent,
.irq_set_affinity = msi_domain_set_affinity,
.irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_compose_msi_msg = irq_msi_compose_msg,
.irq_write_msi_msg = hpet_msi_write_msg,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
@@ -479,13 +476,10 @@ struct irq_domain *hpet_create_irq_domai
info.type = X86_IRQ_ALLOC_TYPE_HPET;
info.hpet_id = hpet_id;
parent = irq_remapping_get_ir_irq_domain(&info);
- if (parent == NULL) {
+ if (parent == NULL)
parent = x86_vector_domain;
- } else {
+ else
hpet_msi_controller.name = "IR-HPET-MSI";
- /* Temporary fix: Will go away */
- hpet_msi_controller.irq_compose_msi_msg = NULL;
- }
fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
hpet_id);
@@ -823,6 +823,7 @@ static struct irq_chip lapic_controller
.name = "APIC",
.irq_ack = apic_ack_edge,
.irq_set_affinity = apic_set_affinity,
+ .irq_compose_msi_msg = x86_vector_msi_compose_msg,
.irq_retrigger = apic_retrigger_irq,
};
Composing the MSI message at the MSI chip level is wrong because the underlying parent domain is the one which knows how the message should be composed for the direct vector delivery or the interrupt remapping table entry. The interrupt remapping aware PCI/MSI chip does that already. Make the direct delivery chip do the same and move the composition of the direct delivery MSI message to the vector domain irq chip. This prepares for the upcoming device MSI support to avoid having architecture specific knowledge in the device MSI domain irq chips. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- V2: New patch --- arch/x86/include/asm/apic.h | 8 ++++++++ arch/x86/kernel/apic/msi.c | 12 +++--------- arch/x86/kernel/apic/vector.c | 1 + 3 files changed, 12 insertions(+), 9 deletions(-)