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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Gb2pmxF+aMeLd7tJRs/LNeeBQ4qY8d0Asrdtw+zUKBA=; b=KHLO+YqMYF4XG4otabAxrWwpJJSJg7fPvWYEo0b972lR31lonsBRmqV9EOyoz1Iz9fC2SOgILPz0CxDkUhBAp+/nowXxpzlysl33ySVrnJ5kzPalNNYF6lhmqUy8OG18VIU/UIC8WewTT3rCfOujHMC84nUZ8DroPD9n1OBNoJ8= From: Roger Pau Monne To: CC: Roger Pau Monne , Jan Beulich , Andrew Cooper , Wei Liu Subject: [PATCH v2 3/4] x86/vpic: issue dpci EOI for cleared pins at ICW1 Date: Fri, 15 Jan 2021 15:28:19 +0100 Message-ID: <20210115142820.35224-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115142820.35224-1-roger.pau@citrix.com> References: <20210115142820.35224-1-roger.pau@citrix.com> X-ClientProxiedBy: MR2P264CA0029.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500::17) To DS7PR03MB5608.namprd03.prod.outlook.com (2603:10b6:5:2c9::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e0fb6cd7-47a3-4c8a-ba79-08d8b961eb5b X-MS-TrafficTypeDiagnostic: DM6PR03MB4137: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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Not doing so can bring the interrupt controller state out of sync with the dpci handling logic, that expects a notification when a pin has been EOI'ed. Fixes: 7b3cb5e5416 ('IRQ injection changes for HVM PCI passthru.') Signed-off-by: Roger Pau Monné --- xen/arch/x86/hvm/vpic.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/x86/hvm/vpic.c b/xen/arch/x86/hvm/vpic.c index c1c1de7fd0..522cacdc4b 100644 --- a/xen/arch/x86/hvm/vpic.c +++ b/xen/arch/x86/hvm/vpic.c @@ -193,6 +193,8 @@ static void vpic_ioport_write( { if ( val & 0x10 ) { + unsigned int pending = vpic->isr | (vpic->irr & ~vpic->elcr); + /* ICW1 */ /* Clear edge-sensing logic. */ vpic->irr &= vpic->elcr; @@ -217,6 +219,24 @@ static void vpic_ioport_write( } vpic->init_state = ((val & 3) << 2) | 1; + vpic_update_int_output(vpic); + vpic_unlock(vpic); + + /* + * Forward the EOI of any pending or in service interrupt that has + * been cleared from IRR or ISR, or else the dpci logic will get + * out of sync with the state of the interrupt controller. + */ + while ( pending ) + { + unsigned int pin = __scanbit(pending, 8); + + ASSERT(pin < 8); + hvm_dpci_eoi(current->domain, + hvm_isa_irq_to_gsi((addr >> 7) ? (pin | 8) : pin)); + __clear_bit(pin, &pending); + } + goto unmask; } else if ( val & 0x08 ) { @@ -306,6 +326,7 @@ static void vpic_ioport_write( vpic_unlock(vpic); + unmask: if ( unmasked ) pt_may_unmask_irq(vpic_domain(vpic), NULL); }